NXP Semiconductors i.MX 8MDQLQ User Manual

© 2019 NXP B.V.i.MX 8MDQLQ Hardware Developer’s Guide1. OverviewThis document aims to help hardware engineers designand test the i.MX 8MDQLQ series processor. It givesexamples on board layout, design checklists to ensurefirst-pass success, and solutions to avoid board bring-upproblems.Engineers should understand board layouts and boardhardware terminology.This guide is released with relevant device-specifichardware documentation such as datasheets, referencemanuals, and application notes. All these documents areavailable on www.nxp.com/i.MX8M.NXP SemiconductorsUser's GuideDocument Number: IMX8MDQLQHDGRev. 2 , 06/2019Contents1. Overview............................................................................ 11.1. Device supported .................................................... 21.2. Essential references................................................. 21.3. Supplementary references ....................................... 21.4. Related documentation............................................ 31.5. Conventions ............................................................ 31.6. Acronyms and abbreviations................................... 42. i.MX 8MDQLQ design checklist ....................................... 52.1. Design checklist table ............................................. 52.2. JTAG signal termination ....................................... 103. i.MX 8MDQLQ layout/routing recommendations ........... 113.1. Introduction........................................................... 113.2. Basic design recommendations ............................. 113.3. Stack-up recommendations ................................... 123.4. DDR design recommendations ............................. 123.5. Trace impedance recommendations ...................... 333.6. Power connectivity/routing ................................... 353.7. USB connectivity .................................................. 373.8. HDMI port connectivity (i.MX 8MDQLQ) .......... 383.9. PCIE connectivity ................................................. 403.10. Unused input/output terminations ......................... 424. Avoiding board bring-up problems .................................. 434.1. Introduction........................................................... 434.2. Avoiding power pitfalls -Current .......................... 434.3. Avoiding power pitfall -Voltage ........................... 434.4. Checking for clock pitfalls .................................... 444.5. Avoiding reset pitfalls ........................................... 454.6. Sample board bring-up checklist........................... 455. Using BSDL for board-level test...................................... 475.1. BSDL overview .................................................... 475.2. How BSDL functions............................................ 475.3. Downloading BSDL files ...................................... 475.4. Pin coverage of BSDL .......................................... 475.5. Boundary scan operation....................................... 485.6. I/O pin power considerations ................................ 486. Revision history ............................................................... 49