<span role="presentation" dir="ltr" style="top:86.84%; left:58.21%">SCB-68A</span>

National Instruments 60 Series Note To Users

PCI-MIO-16E-1

important information

organization of this manual

conventions used in this manual

About the PCI E Series

What You Need to Get Started

National Instruments Application Software

NI-DAQ, and Your Hardware

Register-Level Programming

Custom Cabling

Unpacking

Software Installation

Board Configuration

Figure 3-1. PCI-MIO-16E-1, PCI-MIO-16E-4 and PCI-6071E Block Diagram

Figure 3-2. PCI-MIO-16XE-10 and PCI-6031E Block Diagram

Figure 3-3. PCI-6032E and PCI-6033E Block Diagram

Analog Input

Input Polarity and Input Range

Considerations for Selecting Input Ranges

Dither

Multichannel Scanning Considerations

Analog Output

Analog Output Reglitch Selection

Analog Trigger

Figure 3-7. Below-Low-Level Analog Triggering Mode

Figure 3-9. Inside-Region Analog Triggering Mode

Digital I/O

Figure 3-12. CONVERT* Signal Routing

Programmable Function Inputs

Figure 3-13. RTSI Bus Signal Connection

I/O Connector

PCI-MIO-16E-4, PCI-MIO-16XE-50, PCI-MIO-16XE-10 and PCI-6032E

Figure 4-2. I/O Connector Pin assignment for the PCI-6071E, 6031E and 6033E

I/O Connector Signal Descriptions

Analog Input Signal Connections

Figure 4-3. PCI E Series PGIA

Types of Signal Sources

Figure 4-4. Summary of Analog Input Connections

Differential Connection Considerations (DIFF Input Configuration)

Differential Connections for Ground-Referenced Signal Sources

Differential Connections for Nonreferenced or Floating Signal Sources

Single-Ended Connection Considerations

Figure 4-7. Single-Ended Input Connections for Nonreferenced or Floating Signals

Common-Mode Signal Rejection Considerations

Analog Output Signal Connections

Digital I/O Signal Connections

Figure 4-10. Digital I/O Connections

Power Connections

Programmable Function Input Connections

DAQ Timing Connections

SCANCLK Signal

TRIG1 Signal

TRIG2 Signal

Figure 4-18. TRIG2 Input Signal Timing

STARTSCAN Signal

CONVERT* Signal

Figure 4-22. CONVERT* Input Signal Timing

AIGATE Signal

Waveform Generation Timing Connections

UPDATE* Signal

UISOURCE Signal

General-Purpose Timing Signal Connections

GPCTR0_GATE Signal

GPCTR0_OUT Signal

GPCTR1_SOURCE Signal

GPCTR1_OUT Signal

GPCTR1_UP_DOWN Signal

FREQ_OUT Signal

Loading Calibration Constants

Self-Calibration

Other Considerations

specifications

bus interface

input characteristics

Figure B-1. 68-Pin E Series Connector Pin Assignments

Figure B-2. 68-Pin Extended Analog Input Connector Pin Assignments

Figure B-3. 50-Pin E Series Connector Pin Assignments

Figure B-4. 50-Pin Extended Analog Input Connector Pin Assignments

general information

installation and configuration

technical support form

General Characteristics

Functional Overview

Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram

Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram

Figure 2-4. PCI-6032E and PCI-6033E Block Diagram

Figure 2-5. PCI-MIO-16XE-50 Block Diagram

PCI Interface Circuitry

Analog Input and Timing Circuitry

Analog Input Circuitry

Table 2-1. PGIA Gain Set Verses Board

Single-Read Timing

Data Acquisition Sequence Timing

Figure 2-9. Timing of Scan in Example 1

Figure 2-10. Multirate Scanning of Two Channels

Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate

Figure 2-14. Multirate Scanning without Ghost

Posttrigger and Pretrigger Acquisition

Analog Triggering

Analog Output and Timing Circuitry

Analog Output Circuitry

Single-Point Output

Waveform Generation

Digital I/O Circuitry

RTSI Bus Interface Circuitry

Figure 2-19. RTSI Bus Interface Circuitry Block Diagram

Register Map

Table 3-1. PCI E Series Register Map

Register Sizes

Misc Command Register

Status Register

Analog Input Register Group

ADC FIFO Data Register

Configuration Memory Low Register

Table 3-3. PGIA Gain Selection

Configuration Memory High Register

Table 3-4. Calibration Channel Assignments

Table 3-5. Differential Channel Assignments

Table 3-7. Referenced Single-Ended Channel Assignments

Analog Output Register Group

AO Configuration Register

DAC FIFO Data Register

DAC0 Direct Data Register

DAC1 Direct Data Register

DMA Control Register Group

AI AO Select Register

G0 G1 Select Register

DAQ-STC Register Group

PCl Local Bus

PCI Initialization for the IBM Compatible System

Re-mapping the PCI E Series Board

PCI Initialization for the Macintosh

Windowing Registers

Example 1

Example 2

Example 3

Example Program

Example 4

Programming the MITE for Different DMA Transfers

Example 5

Example 6

Example 7

Example 8

Example 9

General-Purpose Counter/Timer

RTSI Trigger Lines Programming Considerations

Figure 4-1. Analog Trigger Structure

Interrupt Programming

DMA Programming

The Link Chaining Mode for DMA Transfer

Figure 4-3. DMA Link Chaining Mode Structure

About the EEPROM

Figure 5-1. EEPROM Read Timing

Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map

Table 5-2. PCI-MIO-16XE-50 EEPROM Map

Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E and PCI-6033E EEPROM Map

Table 5-4. PCI-6023E EEPROM Map

Table 5-5. PCI-6024E and PCI-6025E EEPROM Map

Table 5-6. PCI-6052E EEPROM Map

Calibration DACs

Figure 5-2. Calibration AC Write Timing

NI-DAQ Calibration Function

PCI-MIO-16E-4

PCI-MIO-16XE-10

PCI-MIO-16XE-50

60 E Series

60 Series

NI 6011E

NI 6013

NI 6014

NI 6015

NI 6020E

NI 6023E

NI 6024E

NI 6030E

NI 6032E

NI 6034E

NI 6035E

NI 6036E

NI 6040E

NI 6052E

NI 6062E

NI 6070E

PCI-6011E

PCI-6030E

PCI-6040E

PCI-6070E