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National Instruments PCI-MIO-16E-4 manuals

PCI-MIO-16E-4 first page preview

PCI-MIO-16E-4

Brand: National Instruments | Category: Control Unit
PCI-MIO-16E-4 first page preview

PCI-MIO-16E-4

Brand: National Instruments | Category: Computer Hardware
Table of contents
  1. important information
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. organization of this manual
  8. conventions used in this manual
  9. related documentation
  10. About the PCI E Series
  11. What You Need to Get Started
  12. National Instruments Application Software
  13. NI-DAQ, and Your Hardware
  14. Register-Level Programming
  15. Custom Cabling
  16. Unpacking
  17. Software Installation
  18. Board Configuration
  19. Figure 3-1. PCI-MIO-16E-1, PCI-MIO-16E-4 and PCI-6071E Block Diagram
  20. Figure 3-2. PCI-MIO-16XE-10 and PCI-6031E Block Diagram
  21. Figure 3-3. PCI-6032E and PCI-6033E Block Diagram
  22. Analog Input
  23. Input Polarity and Input Range
  24. Considerations for Selecting Input Ranges
  25. Dither
  26. Multichannel Scanning Considerations
  27. Analog Output
  28. Analog Output Reglitch Selection
  29. Analog Trigger
  30. Figure 3-7. Below-Low-Level Analog Triggering Mode
  31. Figure 3-9. Inside-Region Analog Triggering Mode
  32. Digital I/O
  33. Figure 3-12. CONVERT* Signal Routing
  34. Programmable Function Inputs
  35. Figure 3-13. RTSI Bus Signal Connection
  36. I/O Connector
  37. PCI-MIO-16E-4, PCI-MIO-16XE-50, PCI-MIO-16XE-10 and PCI-6032E
  38. Figure 4-2. I/O Connector Pin assignment for the PCI-6071E, 6031E and 6033E
  39. I/O Connector Signal Descriptions
  40. Analog Input Signal Connections
  41. Figure 4-3. PCI E Series PGIA
  42. Types of Signal Sources
  43. Figure 4-4. Summary of Analog Input Connections
  44. Differential Connection Considerations (DIFF Input Configuration)
  45. Differential Connections for Ground-Referenced Signal Sources
  46. Differential Connections for Nonreferenced or Floating Signal Sources
  47. Single-Ended Connection Considerations
  48. Figure 4-7. Single-Ended Input Connections for Nonreferenced or Floating Signals
  49. Common-Mode Signal Rejection Considerations
  50. Analog Output Signal Connections
  51. Digital I/O Signal Connections
  52. Figure 4-10. Digital I/O Connections
  53. Power Connections
  54. Programmable Function Input Connections
  55. DAQ Timing Connections
  56. SCANCLK Signal
  57. TRIG1 Signal
  58. TRIG2 Signal
  59. Figure 4-18. TRIG2 Input Signal Timing
  60. STARTSCAN Signal
  61. CONVERT* Signal
  62. Figure 4-22. CONVERT* Input Signal Timing
  63. AIGATE Signal
  64. Waveform Generation Timing Connections
  65. UPDATE* Signal
  66. UISOURCE Signal
  67. General-Purpose Timing Signal Connections
  68. GPCTR0_GATE Signal
  69. GPCTR0_OUT Signal
  70. GPCTR1_SOURCE Signal
  71. GPCTR1_OUT Signal
  72. GPCTR1_UP_DOWN Signal
  73. FREQ_OUT Signal
  74. Loading Calibration Constants
  75. Self-Calibration
  76. Other Considerations
  77. specifications
  78. bus interface
  79. input characteristics
  80. Figure B-1. 68-Pin E Series Connector Pin Assignments
  81. Figure B-2. 68-Pin Extended Analog Input Connector Pin Assignments
  82. Figure B-3. 50-Pin E Series Connector Pin Assignments
  83. Figure B-4. 50-Pin Extended Analog Input Connector Pin Assignments
  84. general information
  85. installation and configuration
  86. technical support form
PCI-MIO-16E-4 first page preview

PCI-MIO-16E-4

Brand: National Instruments | Category: I/O Systems
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. General Characteristics
  8. Functional Overview
  9. Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram
  10. Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram
  11. Figure 2-4. PCI-6032E and PCI-6033E Block Diagram
  12. Figure 2-5. PCI-MIO-16XE-50 Block Diagram
  13. PCI Interface Circuitry
  14. Analog Input and Timing Circuitry
  15. Analog Input Circuitry
  16. Table 2-1. PGIA Gain Set Verses Board
  17. Single-Read Timing
  18. Data Acquisition Sequence Timing
  19. Figure 2-9. Timing of Scan in Example 1
  20. Figure 2-10. Multirate Scanning of Two Channels
  21. Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate
  22. Figure 2-14. Multirate Scanning without Ghost
  23. Posttrigger and Pretrigger Acquisition
  24. Analog Triggering
  25. Analog Output and Timing Circuitry
  26. Analog Output Circuitry
  27. Single-Point Output
  28. Waveform Generation
  29. Digital I/O Circuitry
  30. RTSI Bus Interface Circuitry
  31. Figure 2-19. RTSI Bus Interface Circuitry Block Diagram
  32. Register Map
  33. Table 3-1. PCI E Series Register Map
  34. Register Sizes
  35. Misc Command Register
  36. Status Register
  37. Analog Input Register Group
  38. ADC FIFO Data Register
  39. Configuration Memory Low Register
  40. Table 3-3. PGIA Gain Selection
  41. Configuration Memory High Register
  42. Table 3-4. Calibration Channel Assignments
  43. Table 3-5. Differential Channel Assignments
  44. Table 3-7. Referenced Single-Ended Channel Assignments
  45. Analog Output Register Group
  46. AO Configuration Register
  47. DAC FIFO Data Register
  48. DAC0 Direct Data Register
  49. DAC1 Direct Data Register
  50. DMA Control Register Group
  51. AI AO Select Register
  52. G0 G1 Select Register
  53. DAQ-STC Register Group
  54. PCl Local Bus
  55. PCI Initialization for the IBM Compatible System
  56. Re-mapping the PCI E Series Board
  57. PCI Initialization for the Macintosh
  58. Windowing Registers
  59. Digital I/O
  60. Analog Input
  61. Example 1
  62. Example 2
  63. Example 3
  64. Example Program
  65. Example 4
  66. Programming the MITE for Different DMA Transfers
  67. Example 5
  68. Example 6
  69. Example 7
  70. Example 8
  71. Example 9
  72. Analog Output
  78. General-Purpose Counter/Timer
  81. RTSI Trigger Lines Programming Considerations
  82. Figure 4-1. Analog Trigger Structure
  83. Interrupt Programming
  84. DMA Programming
  85. The Link Chaining Mode for DMA Transfer
  86. Figure 4-3. DMA Link Chaining Mode Structure
  87. About the EEPROM
  88. Figure 5-1. EEPROM Read Timing
  89. Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map
  90. Table 5-2. PCI-MIO-16XE-50 EEPROM Map
  91. Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E and PCI-6033E EEPROM Map
  92. Table 5-4. PCI-6023E EEPROM Map
  93. Table 5-5. PCI-6024E and PCI-6025E EEPROM Map
  94. Table 5-6. PCI-6052E EEPROM Map
  95. Calibration DACs
  96. Figure 5-2. Calibration AC Write Timing
  97. NI-DAQ Calibration Function
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PCI-MIO-16E-1PCI-MIO-16XE-10PCI-MIO-16XE-50PCI-485PCI-1407PCI-6036EPCI-DIO-96DAQ PCI-1200PCI-232PCI-CAN
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