National Instruments NI 5791R User Manual And Specifications

National Instruments NI 5791R User Manual And Specifications Manual pdf 20 page image

The edge is synchronized at the next CPTR edge. After all the device CPTRs are aligned, anedge sent out on the FPGA I/O lines is read at the same clock cycle across all the devices.Note The quality of synchronization is only as good as the quality of SampleClock locking. Some static skew may exist. You can calibrate to eliminate this skewif necessary.The following figure shows the relationship between the time that the master device reads aReference Trigger (Ref Trig) and the time that all the devices read the synchronized version ofthe Reference Trigger (Synchronized Ref Trig). This synchronization requires CPTR alignmenton all the devices.Figure 8. Reading the Reference TriggersSynchronized Ref TrigCPTR Device BRef TrigCPTR Device ASample ClockSynchronization ChecklistVerify that the project settings in the system, the project, the host VI, and the FPGA VI areconfigured as follows.• System settings:– Route the FPGA I/O lines to all the devices.– Depending on your chassis size, you may have to route PXI trigger lines usingMeasurement & Automation Explorer (MAX). Refer to the Measurement &Automation Explorer (MAX) Help at ni.com/manuals for more information aboutrouting PXI trigger lines with MAX.• Project settings:– Configure the adapter module IoModSyncClock (either PXI_CLK10 or DStarA) ifyou are not driving the adapter module CLK IN connector.– Add the FPGA Reference Clock.– Configure the Reference Clock to have zero synchronization registers. In the FPGAIO Property dialog box, set Number of Synchronization Registers for Read to 0.– Add the FPGA I/O lines that you are synchronizing. Do not remove synchronizationregisters.• Host VI:– Configure the adapter module clock source based on the project settings.– Lock the adapter module clock to the clock source.20 | NI 5791R User Manual and Specifications | ni.com