Chapter 4 Analog Input© National Instruments Corporation 4-27 NI 6232/6233 User ManualOther Timing RequirementsThe sample and conversion level timing of M Series devices work such thatclock signals are gated off unless the proper timing requirements are met.For example, the device ignores both ai/SampleClock and ai/ConvertClockuntil it receives a valid ai/StartTrigger signal. When the device recognizesan ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulsesuntil it receives the correct number of ai/ConvertClock pulses.Similarly, the device ignores all ai/ConvertClock pulses until it recognizesan ai/SampleClock pulse. When the device receives the correct number ofai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses untilit receives another ai/SampleClock. Figure 4-13 shows timing sequencesfor a four-channel acquisition (using AI channels 0, 1, 2, and 3) anddemonstrates proper and improper sequencing of ai/SampleClock andai/ConvertClock.It is also possible to use a single external signal to drive bothai/SampleClock and ai/ConvertClock at the same time. In this mode, eachtick of the external clock will cause a conversion on the ADC. Figure 4-13shows this timing relationship.Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClockSimultaneouslyAI Convert Clock Timebase SignalThe AI Convert Clock Timebase (ai/ConvertClockTimebase) signal isdivided down to provide on of the possible sources for ai/ConvertClock.Use one of the following signals as the source ofai/ConvertClockTimebase:• ai/SampleClockTimebase• 20 MHz TimebaseOne External Signal Driving Both Clocksai/SampleClockai/ConvertClockSample #1 Sample #2 Sample #31 2 30 1 2 30 1 …0Channel Measured
