Chapter 10 Digital Routing and Clock GenerationNI 6238/6239 User Manual 10-8 ni.comPXI_CLK10PXI_CLK10 is a common low-skew 10 MHz clock reference clock forsynchronization of multiple modules in a PXI measurement or controlsystem. The PXI backplane is responsible for generating PXI_CLK10independently to each peripheral slot in a PXI chassis.PXI TriggersA PXI chassis provides eight bused trigger lines to each module in asystem. Triggers may be passed from one module to another, allowingprecisely timed responses to asynchronous external events that are beingmonitored or controlled. Triggers can be used to synchronize the operationof several different PXI peripheral modules.On M Series devices, the eight PXI trigger signals are synonymous withRTSI <0..7>.Note that in a PXI chassis with more than eight slots, the PXI trigger linesmay be divided into multiple independent buses. Refer to thedocumentation for your chassis for details.PXI_STAR TriggerIn a PXI system, the Star Trigger bus implements a dedicated trigger linebetween the first peripheral slot (adjacent to the system slot) and the otherperipheral slots. The Star Trigger can be used to synchronize multipledevices or to share a common trigger signal among devices.A Star Trigger controller can be installed in this first peripheral slot toprovide trigger signals to other peripheral modules. Systems that do notrequire this functionality can install any standard peripheral module in thisfirst peripheral slot.An M Series device receives the Star Trigger signal (PXI_STAR) from aStar Trigger controller. PXI_STAR can be used as an external source formany AI, AO, and counter signals.An M Series device is not a Star Trigger controller. An M Series devicemay be used in the first peripheral slot of a PXI system, but the system willnot be able to use the Star Trigger feature.PXI_STAR FiltersYou can enable a programmable debouncing filter on each PFI, RTSI, orPXI_STAR signal. When the filters are enabled, your device samples the
