Chapter 5 Counters© National Instruments Corporation 5-3 Analog Output Series User Manualbut with the source signal inverted and referenced to the falling edge of thesource signal, applies when you program the counter to count falling edges.The gate input timing parameters are referenced to the signal at thesource input or to one of the internally generated signals on your device.Figure 5-2 shows the gate signal referenced to the rising edge of a sourcesignal. The gate must be valid (either high or low) for at least 10 ns beforethe rising or falling edge of a source signal so the gate can take effect at thatsource edge, as shown by t gsu and t gh. The gate signal is not required afterthe active edge of the source signal.If you use an internal timebase clock, you cannot synchronize the gatesignal with the clock. In this case, gates applied close to a source edge takeeffect either on that source edge or on the next one. This arrangementresults in an uncertainty of one source clock period with respect tounsynchronized gating sources.The output timing parameters are referenced to the signal at the sourceinput or to one of the internally generated clock signals on your device.Figure 5-2 shows the out signal referenced to the rising edge of a sourcesignal. Any out signal state changes occur within 80 ns after the rising orfalling edge of the source signal.For information on the internal routing available on the DAQ-STCcounter/timers, refer to Counter Parts in NI-DAQmx in the NI-DAQmxHelp or the LabVIEW Help in version 8.0 for more information.Counter 0 Source SignalYou can select any PFI as well as many other internal signals as the Counter0 Source (Ctr0Source) signal. The Ctr0Source signal is configured inedge-detection mode on either the rising or falling edge. The selected edgeof the Ctr0Source signal increments and decrements the counter valuedepending on the application the counter is performing.You can export the Ctr0Source signal to the PFI 8/CTR 0 SOURCE pin,even if another PFI is inputting the Ctr0Source signal. This output is set tohigh-impedance at startup.