Chapter 3 Signal Connections© National Instruments Corporation 3-11 PCI-DIO-96/PXI-6508/PCI-6503 User ManualHowever, ensure the resistor value is not so large that leakage current fromthe DIO line along with the current from the 100 kΩ pull-up resistor drivesthe voltage at the resistor above a TTL low level of 0.4 VDC.Figure 3-5. DIO Channel Configured for High DIO Power-up State with External LoadExample:By default, all DIO lines are pulled high at power up. To pull one channellow, complete the following steps:1. Install a load (R L ). Remember that the smaller the resistance, thegreater the current consumption and the lower the voltage.2. Using the following formula, calculate the largest possible load tomaintain a logic low level of 0.4 V and supply the maximum drivingcurrent:V = I × R L R L = V/I,where V = 0.4 V; Voltage across RLI = 46 μA + 10 μA; 4.6 V across the 100 kΩ pull-up resistorand 10 μA maximum leakage current(except lines PC0 andPC3)therefore R L = 7.1 kΩ; 0.4 V/56 μAThis resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO lineat power up. You can substitute smaller resistor values to lower the voltageor to provide a margin for Vcc variations and other factors. However,smaller values draw more current, leaving less drive current for othercircuitry connected to this line. The 7.1 kΩ resistor reduces the amount oflogic high source current by 0.4 mA with a 2.8 V output.The maximum leakage current on most lines is 10 μA. The maximumleakage current on the PC(0) and PC(3) lines is 20 μA.DIO BoardDigital I/O Line82C55100 kΩGNDR L+5 V
