National Instruments PXI-6683 Series User Manual

Also see for PXI-6683 Series: Installation guide User manual

Contents

The signal source for each PFI trigger line configured as an output can be independentlyselected from one of the following options:• Another PFI<0..2>• PXI_TRIG<0..7>• PXI_STAR<0..12> (PXI-6683 only)• Future time events• PXI_CLK10• GroundTip Invert Ground to get a logic high.The PFI trigger outputs may be synchronized to CLK10 except when routing future timeevents. Refer to the Choosing the Type of Routing section for more information about thesynchronization clock.Using Front Panel PFI Terminals as InputsThe front panel PFI terminals can be configured by software to accept input signals. Refer tothe NI-Sync documentation for information on how to set up the PFI terminals to accept inputsignals. You can use these terminals to timestamp triggers with the synchronized system timeor to route signals to other destinations (refer to Table 7. on page 16). The input terminalsaccept native +3.3 V signaling, but are +5 tolerant. Use 50 Ω source termination when drivingsignals into PFI terminals.The voltage thresholds for the front panel PFI input signals are fixed. Refer to the PXI-6683Series Specifications for the voltage thresholds. The front panel PFI input signals can betimestamped on rising, falling, or both edges of an input signal.PFI0 and SSR SwitchingSince PFI0 is a dual-purpose terminal capable of performing digital I/O like the other PFI lineswhile also being capable of receiving IRIG-B AM and DC inputs, care is taken to protect thedigital circuitry when PFI0 is being used as an IRIG-B AM input. This is achieved with anormally-open solid-state relay (SSR), which is closed only when digital operations for theline are enabled through the API. Digital operations include setting up routes in which PFI0 isthe source or the destination, enabling timestamping for PFI0, scheduling future time events orclocks for PFI0, and setting IRIG-B DC as the time reference.The SSR has a 5 ms open and close time. Therefore, care must be taken when using PFI0 toensure correct operation when the SSR is switching.To avoid issues due to the SSR switching, follow these guidelines:• Whenever timestamping begins on PFI0, either ensure the input will remain at a logiclow state for at least 5 ms or disregard timestamps for at least 5 ms.• When setting up PFI0 as an output (future time events or clocks), ensure that PFI0 isdriven low for at least 5 ms after the line is set up. Alternately, ensure that the externalreceiver can tolerate a slow rising edge.PXI-6683(H) User Manual | © National Instruments | 17