5-32 | ni.comChapter 5 CountersPulse Generation for ETSIn the equivalent time sampling (ETS) application, the counter produces a pulse on the output aspecified delay after an active edge on Gate. After each active edge on Gate, the countercumulatively increments the delay between the Gate and the pulse on the output by a specifiedamount. Thus, the delay between the Gate and the pulse produced successively increases.The increase in the delay value can be between 0 and 255. For instance, if you specify theincrement to be 10, the delay between the active Gate edge and the pulse on the output increasesby 10 every time a new pulse is generated.Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10.On the first trigger, your pulse delay will be 100, on the second it will be 110, on the third it willbe 120; the process will repeat in this manner until the counter is disarmed. The counter ignoresany Gate edge that is received while the pulse triggered by the previous Gate edge is in progress.The waveform thus produced at the counter’s output can be used to provide timing forundersampling applications where a digitizing system can sample repetitive waveforms that arehigher in frequency than the Nyquist frequency of the system. Figure 5-36 shows an example ofpulse generation for ETS; the delay from the trigger to the pulse increases after each subsequentGate active edge.Figure 5-36. Pulse Generation for ETSFor information about connecting counter signals, refer to the Default Counter/Timer Routingsection.Counter Timing SignalsThe cDAQ controller features the following counter timing signals:• Counter n Source Signal• Counter n Gate Signal• Counter n Aux Signal• Counter n A Signal• Counter n B Signal• Counter n Z Signal• Counter n Up_Down SignalOUTD1 D2 = D1 + DD D3 = D1 + 2DDGATE
