The figure below shows an example of a sample clocked buffered two-signal separationmeasurement.Figure 73. Sample Clocked Buffered Two-Signal Separation MeasurementSOURCECounter ValueBufferAUXGATE1 2 3 1 2 3 1 2 33 33SampleClockNote If an active edge on the Gate and an active edge on the Aux does not occurbetween sample clocks, an overrun error occurs.For information about connecting counter signals, refer to the Default Counter/Timer Routingsection.Counter Output ApplicationsThe following sections list the various counter output applications available on the cRIOcontroller:• Simple Pulse Generation• Pulse Train Generation• Frequency Generation• Frequency Division• Pulse Generation for ETSSimple Pulse GenerationRefer to the following sections for more information about the cRIO controller simple pulsegeneration options:• Single Pulse Generation• Single Pulse Generation with Start TriggerSingle Pulse GenerationThe counter can output a single pulse. The pulse appears on the Counter n Internal Outputsignal of the counter.You can specify a delay from when the counter is armed to the beginning of the pulse. Thedelay is measured in terms of a number of active edges of the Source input.cRIO-904x User Manual | © National Instruments | 97