National Semiconductor ADC10080 Manual
Also see for ADC10080: User guide
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Functional DescriptionThe ADC10080 uses a pipeline architecture and has errorcorrection circuitry to help ensure maximum performance.Differential analog input signals are digitized to 10 bits. In dif-ferential mode each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending onthe state of the IRS pin (pin 5), and be centered around VCMand be 180° out of phase with each other. If single endedoperation is desired, VIN- may be tied to the VCOM pin (pin 4).A single ended input signal may then be applied to VIN+, andshould have a mid range value of VCOM. The signal amplitudeshould be 2.0V, 1.5V or 1.0V peak-to-peak, depending on thestate or the IRS pin (pin 5).Applications Information1.0 ANALOG INPUTSThe ADC10080 has two analog signal inputs, VIN+ and VIN−.These two pins form a differential input pair. There is onecommon mode pin VCOM that may be used to set the commonmode input voltage.1.1 REFERENCE PINSThe ADC10080 is designed to operate with a 1.2V reference.The voltages at VCOM, VREFT, and VREFB are derived from thereference voltage. It is very important that all grounds asso-ciated with the reference voltage and the input signal makeconnection to the analog ground plane at a single point tominimize the effects of noise currents in the ground path. Thethree Reference Bypass Pins VREF, VREFT and VREFB, aremade available for bypass purposes only. These pins shouldeach be bypassed to ground with a 0.1 μF capacitor. DO NOTLOAD these pins.1.2 VCOM PINThis pin supplies a voltage for possible use to set the commonmode input voltage. This pin may also be connected to VIN-,so that VIN+ may be used as a single ended input. This pinshould be bypassed with at least a 0.1 uF capacitor. Do notload this pin.1.3 SIGNAL INPUTSThe signal inputs are VIN+ and VIN−. The input signal ampli-tude is defined as VIN+ − VIN− and is represented in Figure3:20048547FIGURE 3. Input Voltage Waveforms for a 2VP-PDifferential InputA single ended input signal is shown in Figure 4.20048548FIGURE 4. Input Voltage Waveform for a 2VP-P SingleEnded InputThe internal switching action at the analog inputs causes en-ergy to be output from the input pins. As the driving sourcetries to compensate for this, it adds noise to the signal. Toprevent this, use 18Ω series resistors at each of the signalinput pins with a 25 pF capacitor across the inputs, as shownin Figure 5. These components should be placed close to theADC because the input pins of the ADC is the most sensitivepart of the system and this is the last opportunity to filter theinput. The two 18Ω resistors and the 25 pF capacitor form alow-pass filter with a -3 dB frequency of 177 MHz.1.4 CLK PINThe CLK signal controls the timing of the sampling process.Drive the clock input with a stable, low jitter clock signal in thefrequency range indicated in the AC Electrical CharacteristicsTable with rise and fall times of less than 2 ns. The trace car-rying the clock signal should be as short as possible andshould not cross any other signal line, analog or digital, noteven at 90°. The CLK signal also drives an internal state ma-chine. If the CLK is interrupted, or its frequency is too low, thecharge on internal capacitors can dissipate to the point wherethe accuracy of the output data will degrade. This is what limitsthe lowest sample rate. The duty cycle of the clock signal canaffect the performance of any A/D Converter. Becauseachieving a precise duty cycle is difficult, the ADC10080 isdesigned to maintain performance over a range of duty cy-cles. While it is specified and performance is guaranteed witha 50% clock duty cycle, performance is typically maintainedwith minimum clock low and high times indicated in the ACElectrical Characteristics Table. Both minimum high and lowtimes may not be held simultaneously.1.5 STBY PINThe STBY pin, when high, holds the ADC10080 in a power-down mode to conserve power when the converter is notbeing used. The power consumption in this state is 15 mW.The output data pins are undefined in this mode. Power con-sumption during power-down is not affected by the clockfrequency, or by whether there is a clock signal present. Thedata in the pipeline is corrupted while in power down.1.6 DF PINThe DF (Data Format) pin, when high, forces the ADC10080to output the 2’s complement data format. When DF is tiedlow, the output format is offset binary.1.7 IRS PINThe IRS (Input Range Select) pin defines the input signal am-plitude that will produce a full scale output. The table belowdescribes the function of the IRS pin.www.national.com 16ADC10080 |
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