Nautel VS2.5 Troubleshooting Manual

Also see for VS2.5: Installation manual Installation manual Troubleshooting manual

Contents

VS2.5 Troubleshooting Manual Detailed Circuit DescriptionsIssue 4.0 2012-12-01 Page 2-3Fan monitoring8-bit shift register IC U5 accepts the fan tach signals from fans B1 and B2 and converts them to aserial data stream on the MISO 165 output (J2-4). This output is applied to the exciter/control PWBfor monitoring purposes.Power supply combiningResistors R3, R4, R53, R54, R70, R71, R86, R97 and R98 form a circuit that parallel combines theoutputs of the three power supply modules (U1, U2 and U3) such that their output currents addtogether.LVPSTwo +48 V to +5 V dc-dc converters (U16 and U17) and their associated components generate the+5 V rail that is applied to circuitry throughout the transmitter.A +48 V to +15 V converter (U1) and its associated components generate the +15 V that is appliedto the exciter/control PWB.Pre-amp/IPA PWB (NAPA28B)See electrical schematic Figure SD-4.The pre-amp/IPA PWB (A5) accepts the RF output of the exciter/control PWB (A1), or externalsource, and amplifies it to an intermediate RF drive level for application to the PA PWBs (A6through A9) via the splitter PWB (A4). The pre-amp/IPA PWB contains two N-channel FETs (Q1and Q2) and associated components configured as a two-stage RF power amplifier. The RF output isgenerated by the Pre-amp V and IPA V levels provided by the PS distribution PWB (A2), and the Pre-amp Bias and IPA Bias outputs from the exciter/control PWB (A1). The RF output level is controlledby the RF input level generated by the exciter/control PWB. Cooling air for the pre-amp PWB isprovided by fan B1.The RF Drive input is applied to the gate of FET Q1 through a series of micro-strip transmission linesections and capacitors C1 and C2 and inductor L1, which provide impedance matching to transformthe 50 ohm input to low impedance for application to Q1. Additional micro-strip transmission linesections at the output of Q1, as well as inductors L8 and L9 and capacitors C16 and C17, impedancematch the Q1 output signal to 50 ohms. The impedance matched output of Q1 is applied to the gateof FET Q2 through a series of micro-strip transmission line sections and associated components,