Panasonic EB-X400 Service Manual

Also see for EB-X400: Operating instructions Operating instructions

Contents

– 5-6 –■ Clock InterfaceThe U2001 (E-Gold + V3) clock generation unit is used to generate all major system clocks. There are two clock signalsconnected to the clock generation unit.8 32 kHz clock F32K8 26 MHz clock F13/26MThe 32 kHz oscillator is used for the Real Time Clock block. As a power-saving feature the 32 kHz clock can be also used forthe MCU domain. The 32 kHz oscillator and the RTC block have its own power supply pads. It has the facility for a back-uppower source for when the main battery is discharged or remoed temporarily.The 26 MHz clock is used as the major U2001 (E-Gold + V3) clock reference. An on chip shaper is used to maintain thelow-swing input level on F13/26M. It can be powered-up with a delay (programmable in ECO block) related to the TCXOpower-up. This can slightly reduce overall power consumption.CLKCTRL Clock Control RegisterPLLUP : PLL Power Up BitSWCLK : PLL Clock Switch BitCLKAEN : CLKANA Enable BitSXMEN : Coprocessor clock enableSX52M : Coprocessor clock switchAFCEN : AFC Enable BitCPUH : Enables 52 MHz operation of the CPU and serial interfaceCPUPRE [2:0] : CPU Clock Prescale FactorAFC32KEN : AFC clock enable during ECO eco sleeep mode13/26MHz_IN : Configure the CGU for the operation with either 13 MHz or 26 MHz inputCGURST Clock Generation Uint Reset RegisterDSPRST : DSP Reset BitSIMRST : SIM Card Interface Reset BitRTCRST : Real Time Clock Rest BitDSPSLOW : DSP slow-down control bitThe frequency of clk_pll depends on 13/26 MHZ_IN and DSPSLOW refers to the below table.15 14 13 12 11 10 9 813/26 - - AFC32KEN - CPUPRE (2:0)MHz_IN7 6 5 4 3 2 1 0- CPUH AFCEN SX52M SXMEN CLKAEN SWCLK PLLUP15 14 13 12 11 10 9 8DSPSLOW 0 0 0 0 0 r rDSPSLOW 13/26 MHZ_IN Frequency of Input Frequency of Frequency of Frequency ofClock F13/26M clk_pll clk_dsp clk_master0 0 26 MHz 104 MHz 104 MHz 52MHz0 1 13 MHz 104 MHz 104 MHz 52MHz1 0 26 MHz 156 MHz 78 MHz 52MHz1 1 13 MHz 156 MHz 78 MHz 52MHz7 6 5 4 3 2 1 00 0 0 0 RTCRST SIMRST DSPRST