Panasonic G600 Technical Manual

Also see for EB-CR600: Service manual Service manual Service manual

Contents

http://cxema.ru7.2.3 Memory InterfaceThe memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait statesto memory access. The memory interface allows between 0 and 7 wait states to be added. The ROM area ishardware write protected, a FLASH write enable bit in the ROM wait state configuration register can be used toenable write access the ROM area.CPU Memory MAPDevice Name Start address Size Use Bus widthROM 0000:0000 2M FLASH 1M bytes 16 bitsRAM 0020:0000 2M RAM 256k bytes 8 bitsBUS CNTRL 0040:0000 1M wait state registers 16 bitsAPI RAM 0050:0000 8k CPU/DSP shared ram 16 bitsTPU RAM 0050:0000 8k GSM timer Microcode RAM 16 bitsAPIC 0050:4000 1k CPU/DSP interface controller 16 bitsSIM 0050:4800 1k SIM interface 16 bitsTSP 0050:4C00 1k Timed Serial port 16 bitsINTH 0050:5000 1k Interrupt controller 16 bitsTPU REG 0050:5400 1k GSM timer registers 16 bitsCLKM 0050:5800 1k Clock control module 16 bitsTIMER 0050:5C00 1k software timers 16 bitAPIF 0050:6000 1k ARM peripheral interface 16 bitUWIRE 0050:6400 1k Synchronous Serial port 16 bitARMIO 0050:6800 1k Keypad, buzzer, LCD & I/O 8 bit8251 0050:6C00 1k UART 8 bitCS2 0060:0000 2M LCD driver 8 bitnCS0 0080:0000 2M Extended I/O 8 bitnCS1 00A0:0000 2M not used —Issue 1 Section 7 MCUK980101G8Revision 0 7 - 2 Technical GuideGEMINI