7.4. FACSIMILE SECTION7.4.1. IMAGE DATA FLOW DURING FACSIMILE OPERATIONCOPY (Fine, Super-Fine, Half Tone)1. Line information is read by CIS (to be used as the reference white level) via route 1, and is input to IC501. Refer to 6.4.2.Block Diagram.2. In IC501, the data is adjusted to a suitable level for A/D conversion in the Analog Signal Processing Section, and via route2it is input to A/D conversion (8 bit). After finishing A/D conversion, the data is input to the Image Processing Section via route3. Then via routes 4 and 5, it is stored in RAM as shading data.3. The draftÕs information that is read by CIS is input to IC501 via route 1. After it is adjusted to a suitable level for A/Dconversion via route 2, the draftÕs information is converted to A/D (8 bit), and it is input to the Image Processing Section.The other side, the shading data which flows from RAM via routes 6and 7, is input to the Image Processing Section. Afterfinishing the draftÕs information image processing, white is regarded as "0" and black is regarded as "1". Then via routes4and 5, they are stored in RAM.4. The white/black data stored as above via routes 6 and 8 is input to the P/S converter. The white/black data converted toserial data in the P/S converter is input to the Thermal Head via route 9 and is printed out on recording paper.Note:Standard : Reads 3.58 times/mmFine : Reads 7.7 times/mmSuper-Fine : Reads 15.4 times/mmTransmission1. Same processing as COPY items 1 - 3.2. The data stored in the RAM of IC501 is output from IC501 via routes 6 and 10, and is stored in the system bus.Via route 11, it is stored in the communication buffer inside DRAM (IC503).3. While retreiving data stored in the communication buffer synchronous with the modem, the CPU (inside IC501) inputs thedata to the modem along route 12, where it is converted to serial analog data and forwarded over the telephone lines viathe NCU Section.Reception1. The serial analog image data is received over the telephone lines and input to the modem via the NCU section, where it isdemodulated to parallel digital data. Then the CPU (IC501) stores the data in the communication buffer DRAM (IC503)along route 12.2. The data stored in DRAM (IC503) is decoded by the CPU (IC501) via route 12, and is stored in DRAM (IC503) via routes13 and 5.3. Same processing as COPY item 4.161KX-FPC135 / KX-FPC141