70KX-TG7100ES/KX-TG7102ES/KX-TG7103ES/KX-TGA710ES14.2. CPU Data (Handset)14.2.1. IC1 (BBIC)Pin No Description I/O Connection at Normal at Reset mode1 LED1/PWM0/P2[0] D,O LCD_BK O I-PU2 LED2/PWM1/P2[1] D,O LCD_CSB O I-PU3 SK D,O SK O O-L4 SIO D,I/O SIO I/O I-PD5 LE D,I/O LE O O-L6 P3[1]/PD1 D,O COL1 I/O I-PD7 P3[2]/PD2 D,O COL2 I/O I-PD8 TDO A,O TDO O O-L9 RDI D,I RDI I I10 RSSI/RFCLKm A,I RSSI I I11 VSSRF S VSSRF S -12 CAP A,I CAP I I13 Xtal1 A,I Xtal1 I I14 AVS S AVS S -15 AVD_XTAL A,I AVD_XTAL I I16 VDDRF S VDDRF S -17 RFCLKd D,O RFCLK O O-L18 VDDIO S VDDIO S -19 VDD S VDD S -20 VSS S VSS S -21 TDOD/P2[7] D,O NC O I-PU22 SDA1/P2[5] D,IO LCD_SI O I23 SCL1/P2[4] D,IO LCD_SCL O I24 INT5n/P1[5] D,IO LCD_RS O O-H25 INT2n/P1[2] D,IO ROW2 I I-PU26 BXTAL/P5[0] D,IO NC O I-PD27 P4[0] D,IO NC O I-PD28 P4[1] D,IO NC O I-PD29 P4[2] D,IO NC O I-PD30 P4[3] D,IO NC O I-PD31 P4[4] D,IO NC O I-PD32 P4[5] D,IO NC O I-PD33 P4[6] D,IO NC O I-PD34 P4[7] D,IO NC O I-PD35 VSSPA S VSSPA S -36 PAOUTp/P5[2] A,O PAOUTp O O-L37 VDDPA S VDDPA S -38 PAOUTp/P5[1] A,O PAOUTp O O-L39 VSSPA S VSSPA S -40 VSS - VSS S -41 VDDIO - VDDIO S -42 VDD - VDD - -43 PCM1_CLK/P3[3]/PD3 D,O COL3 I/O I44 PCM1_DOUT/P3[4]/PD4 D,O COL4 I/O I45 PCM1_DIN/P3[5]/PD5 D,O COL5 I/O I46 PCM1_FSC/P3[6]/PD6 D,O NC O I47 INT0n/P1[0] D,I ROW0 I I-PU48 SPI2_CLK/P3[7] D,O NC O I-PD49 SPI2_DO/P0[0]/TRAX D,O UTX O I-PU50 SPI2_DI/P0[1]/URX D,O URX I I-PU51 P0[2]/JTIO D,O JTAG I/O I-PU52 P0[3]/SDA2/UTX2 D,IO EEP_SDA I/O I-PU53 P0[4]/SCL2/URX/SPI1_END,O EEP_SCL O I-PU54 P0[5]/SPI1_CLK D,O BELL_LED O I-PU55 P0[6]/SPI1_DO D,O NC O I-PU56 P0[7]/SPI1_DI D,O RF_RESET O I-PU57 VSS S VSS S -58 VDD S VDD S -59 VDDIO S VDDIO S -60 P2[3]/ADC1 D,O EEP_WP O I61 P5[3]/PCM1_CLK D,O NC O I-PU