2-3 Bus Interface2-3-1 OverviewThe MN101C117, unlike other MN101C series microcomputers, does notsupport memory expansion mode and processor mode.2-3-2 Control RegistersThe memory control register is a four-bit register that sets up wait-count at atime of access to a base address of interrupt vector table and a specialregister zone.(1) Memory control register(MEMCTR)Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/WChapter 2 Basic CPU Functions30 Bus Interface7 6 5 4 3 2 1 0MEMCTR IOW1 IOW0 IRWEIRWE Set software write for interrupt request flag01Software write disableEven if data is written to each interrupt controlregister (xxxICR), the state of the interruptrequest flag (xxxIR) will not change.Software write enableIOW1 to 0 Number of wait cycles set whenaccessing special register area00011011No wait cycles1 wait cycle2 wait cycles3 wait cyclesBus cycle at20MHz oscillation100ns150ns200ns250nsIVBAIVBA Base address setting for interrupt vector table0 Interrupt vector base = X'04000'Interrupt vector base = X'00100'1(at reset: 11001011)Must be set to 11.Must be set to 1.Must be set to 0
