Quatech DS-3000 User Manual

Quatech DS-3000 User Manual Manual pdf 4 page image

I . I N T R O D U C T I O NT h e D S - 2 0 0 0 i s a d u a l c h a n n e l a s y n c h r o n o u s s e r i a lc o m m u n i c a t i o n a d a p t e r w h i c h u t i l i z e s b a l a n c e dd i f f e r e n t i a l d r i v e r s a n d r e c e i v e r s t o p r o v i d e R S - 4 2 2 - Acommunications. It is capable of reliable communicationsover long distances (4000 feet) within noisy industriale n v i r o n m e n t . D a t a i s c o m m u n i c a t e d t h r o u g h t w o D - 9c o n n e c t o r s w h i c h p r o v i d e s h i e l d i n g f r o m e n v i r o n m e n t a ln o i s e . O p t i o n a l h i g h s p e e d t r a n s i e n t s u p p r e s s e r s m a ya l s o b e i n s t a l l e d o n t h e D S - 2 0 0 0 t o f u r t h e r r e d u c e t h eeffects of environmental signal transients and surges.The serial interface is accomplished through a pairof 16550 Asynchronous Communication Elements (ACEs). The16550 is compatible with the 8250 and 16450 ACEs used int h e I B M P C / X T / A T m o d e l s . T h e 1 6 5 5 0 a l s o h a s a nadditional FIFO mode that reduces CPU overhead at higherdata rates.The DS-2000 supports sixteen base addresses for eachA C E t h r o u g h t h e P r o g r a m m a b l e O p t i o n S e l e c t ( P O S )including the eight addresses designated SERIAL 1 throughS E R I A L 8 . T h e a d d r e s s e s a r e i n d e p e n d e n t f o r e a c hchannel. CPU interrupt level selections are also handledt h r o u g h t h e P O S . E a c h c h a n n e l m a y s e l e c t a s e p a r a t einterrupt or share an interrupt level with other devices.II. B O A R D D E S C R I P T I O NA c o m p o n e n t d i a g r a m o f t h e D S - 2 0 0 0 s h o w i n g t h el o c a t i o n s o f t h e 1 6 5 5 0 A C E s , c o n f i g u r a t i o n j u m p e r s , a n dD - 9 c o n n e c t o r s i s s h o w n i n f i g u r e 1 . T h e f i r s tcommunication channel is controlled by the 16550 labeledU 9 , j u m p e r J 2 , a n d i s a c c e s s e d t h r o u g h t h e c o n n e c t o rl a b e l e d C N 1 . T h e s e c o n d c h a n n e l u s e s t h e 1 6 5 5 0 l a b e l e dU 1 0 , j u m p e r J 3 , a n d i s a c c e s s e d t h r o u g h t h e c o n n e c t o rlabeled CN2. The clock rate divider for both channels iscontrolled by jumper J1.iii