Contents - Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Document Conventions
- Processor Registers
- OpCode Descriptions
- ADC HL,ss
- ADD A,(HL)
- ADD HL,ss
- ADD IX,xx
- ADD SP,d
- ALTD
- AND (HL)
- AND HL,DE
- BIT b,(HL)
- CP (IX+d)
- DEC (HL)
- EX (SP),HL
- EX (SP),IX
- EX AF,AF
- EX DE,HL
- IDET
- INC (HL)
- IPSET
- IPRES
- LCALL x,mn
- LD (BC),A
- LD (HL+d),HL
- LD (IX+d),r
- LD (IY+d),HL
- LD (mn),A
- LD (SP+n),IX
- LD A,(mn)
- LD A,EIR
- LD A,XPC
- LD dd,(mn)
- LD dd',BC
- LD dd,mn
- LD EIR,A
- LD HL,(mn)
- LD HL,(SP+n)
- LD HL,IX
- LD IX,(mn)
- LD IX,(SP+n)
- LD IX,mn
- LD IY,(mn)
- LD IY,(SP+n)
- LD r,(HL)
- LD SP,IY
- LD XPC,A
- LDDR
- LDISR
- LDP (HL),HL
- LDP (mn),HL
- LDP HL,(HL)
- LDP HL,(mn)
- LJP x,mn
- LRET
- LSDDR
- OR (IX+d)
- OR HL,DE
- OR IX,DE
- RDMODE
- RES b,(HL)
- RETI
- RL (IX+d)
- RLC (HL)
- RLCA
- RR (IX+d)
- RRC (HL)
- RRCA
- SBC (IX+d)
- SBC HL,ss
- SET b,(HL)
- SETUSR
- SLA (HL)
- SRA (HL)
- SRL (HL)
- SUB (HL)
- SURES
- SYSCALL
- XOR (HL)
- Opcode Map
- Quick Reference Table
- Notice to Users
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Instruction Reference Manual 87Description• LDD: Loads the memory location whose address is in DE with the data at the address in HL.Then it decrements the data in BC, DE, and HL.• LDDR: While the data in BC does not equal 0 then the memory location whose address is in DEis loaded with the data at the address in HL. Then it decrements the data in BC, DE, and HL. Theinstruction then repeats until BC equals zero.• LDI: Loads the memory location whose address is in DE with the data at the address in HL.Then the data in BC is decremented and the data in DE and HL is incremented.• LDIR: While the data in BC does not equal 0 then the memory location whose address is in DEis loaded with the data at the address in HL. Then the data in BC is decremented and the data inDE and HL are incremented. The instruction then repeats until BC equals zero.If any of these block move instructions are prefixed by IOI or IOE, the destination will be in the specified I/Ospace. Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2clocks plus the number of I/O wait states enabled. The V flag is cleared when BC transitions from 1 to 0. Ifthe V flag is not cleared another step is performed for the repeating versions of the instructions. Interrupts canoccur between different repeats, but not within an iteration equivalent to LDD or LDI. Return from the inter-rupt is to the first byte of the instruction which is the I/O prefix byte if there is one.LDDLDDRLDILDIROpcode Instruction Clocks OperationED A8 LDD 10 (2,2,1,2,3) (DE) = (HL); BC = BC - 1;DE = DE - 1; HL = HL - 1ED B8 LDDR 6 + 7i (2,2,1,(2,3,2)i,1) repeat:(DE) = (HL); BC = BC - 1;DE = DE - 1; HL = HL - 1until { BC == 0 }ED A0 LDI 10 (2,2,1,2,3) (DE) = (HL); BC = BC - 1;DE = DE + 1; HL = HL + 1ED B0 LDIR 6 + 7i (2,2,1,(2,3,2)i,1) repeat:(DE) = (HL); BC = BC - 1;DE = DE + 1; HL = HL + 1until { BC == 0 }Flags ALTD I/OS Z L/V C F R SP S D- - • - •
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