Rastergraf3-6 Programming On-board Devices3.2.6 Display List ProcessorThe Display List Processor (DLP) is used to feed a set of commands to theDrawing Engine. The DLP uses a 128-bit instruction word. The instructionformats allow for each word to write up to three Drawing Engine registersor two text glyphs. There is a four register mode which only writes XY0,XY1, XY2, and XY3. This mode cannot be mixed with any other mode.3.2.7 CRT ControllerThe CRT Controller provides programmable CRT timing signals:horizontal, vertical blanks and syncs. It is also responsible for generatingrequests to the memory controller for screen refresh cycles. A free runningframe counter which generates interrupts to the Host is also provided. Thisis useful for synchronizing bit map copies. CRT Controller also providesdisplay refresh data for the internal RAMDAC.3.2.8 Memory ControllerThe Memory Controller arbitrates and controls all access to the localmemory buffer by the Host Interface, the CRT controller, and the DrawingEngine. This unit provides support for SGRAM memory.3.2.9 VGA CoreThe Borealis incorporates an IBM-compatible VGA core. The VGA coreimplements the standard VGA register set for the various VGAcomponents (CRT controller, sequencer, graphics controller, attributecontroller, etc.) and is capable generating the standard VGA modes (00h -07h, 00h - 13h). The control of memory and CRT signals can be switchedbetween the VGA core and the Borealis. The VGA memory space isshared with the Borealis frame buffer and is sparsely mapped within it.
