Circuit Description5-10 SF700ATPOWER MONITORIf 5V power to KIA7045F drops to between 4.65and 4.35V (typically 4.5V), power failure will beindicated and the output of KIA7045F will go 'low'(GND). This causes the IFC to become active('low'=reset). The IFC reset causes the MODEMIFC/RESET terminal to be reset. The outputterminal of KIA7045F is an open-drainconfiguration, and is connected to PFC through a10k pull-up resistor.WATCH DOG TIMERThis programmable counter in the IFC is resetevery 2 ms. If not reset after 250 ms, the system isautomatically reset and switches to initialise mode.BATTERY POWER RESETWhen battery power (VB ) is applied to IFC the firsttime, VB current results in /BATRST going 'low',causing a reset to occur.5-2-14 ResetTwo power resets and a watchdog timer in the IFCcomprise the elements of this circuit. Batterypower reset (/BATRST) is used to initialise thebattery-powered logic, and primary power reset(/PWRDWN) initialises non-battery-poweredlogic when system power is supplied.Figure 5-12: Power Reset Block Diagramicik (TSTCLK)Watchdog ResetReset clockresetDividerXOUT/PWRDWNPowerDownNMIPower up Delay 1(1-2 Reset clocks)Power up Delay 2(8 TSTCLKS)vddresnRESETnresnTo internal logicClock enableMC24 NMIroutinesetlockclearLockoutLogiclockoutto battery (BackupConfig) register resetBATRSTnset tristate TristateControlCS0n