SAMSUNG Proprietary-Contents may change without noticeThis Document can not be used without Samsung's authorization5. SGH-P510 Block Diagrams5-1•Clock Generation•ARM/DSP PLL•MP3 PLL•ARM Core•External Bus Interface•Dual Port RAM•DSP Core•Modulator•Tune &Intra framesequencer•status &monitor•rampsequencer•osc•ccxo tune•ClockGeneration•burstsequencer•SerialInterface•DC•RX•serial•Interface•AudioCODECserialInterface muxCX20524CX74063• 900MHz• 1800MHz• 1900MHz•LO•Gen•LO•Gen•DC •DC •DC•Serial controlInterface