Sanyo MCD-ZX300 Service Manual

Contents

- 8 -IC BLOCK DIAGRAM & DESCRIPTIONIC901 TC94A23FN503 (CD PROCESSOR)R/W Buf.Micon interfaceALU78767768 67 66 65 64 63 62 61 60 59 58 55X SSXIXO80XV DD81DV SR82RO83DV RR84DV DD85DV RL86LO87DV SLVDDV SS93MXO94MXI24P1-321P1-092INTR32P4-3(SCK/SCL)31P4-2(S10/S11/SDA)30P4-1(S12)29P4-0(ADin/BUZR)28P3-3(ADin3)27P3-2(ADin2)26P3-1(ADin1)25P3-0BiasLCD Driver/Output Port Port 8Port 2Power on ResetCOM1(OT1) 9897COM2(OT2) 99COM3(OT3) 100COM4(OT4) 1S1(OT5) 2S2(OT6) 10S10(OT14/ZDET) 11S11(OT15/CLCK) 12S12(OT16/DATA) 13S13(OT17/SFSY) 14S14(OT18/LRCK) 15P8-0(S15/BCK) 16P8-1(S16/AOUT) 17P8-2(S17/MBOV) 18P8-3(S18/IPF)36353433P2-3(DATAin)90 RST19,9646,7547,76MVDD20,95 MVSSP2-2(LRCKin)P2-1(HSO in)P2-0(EMPHin)8937IN2IN1(BCKin)38 TESTC88 TESTM91 HOLD39 OT19(HSO)40 OT20(SPCK)41 OT21(SPDA)42 OT22(COFS)43 DOUT44 SBSY45 SBOK50 LPFN51 LPFO53 PVREF54 VCOF48 P2V REF49 PDO50 TMAX56 SLCO57 RFIAVSSAVDDRFCIRFZIRFRPFEISBADTEITEZIFOOTROVREF69 RFGC70 TEBC71 FMO72 DMO73 2V REF74 SELZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPFResetF/FOT19-22Correction circuit16k SRAMAddressStack Reg.(8Level)ADConv.Port 3BUZRPort 4SerialInterfaceInterruptCont.TimerPort 1X’talOSC MPXCPU clockSBSYROM(16 x 8192 Step)Data Reg(16 bit)ProgramCounter InstructionDecoderRAM(4 x 512 word)G-Reg.SBSYCLCK, DATA, SFSY,LRCK, BCK, MBOV, IPFResetCD ResetAudio out Digital outADZDETPWMPX’tal OSCClockgene.1 bit DACRAMLPFROMVREFCLVservo Synchronousguarantee EFMdecodeVCOSub code decoderSERVOcontrolDigital equalizerAutomatic adjustmentcircuitCD clock V REFDADataslicerPLLTMAXVREFP2-0~P2-3IN1