– 3 –Fig. 1-1.Optical Black Location (Top View)Pin No. Symbol Pin Description Waveform VoltageTable 1-1. CCD Pin Description When sensor read-outFig. 1-2. CCD Block Diagram1. OUTLINE OF CIRCUIT DESCRIPTION1-1. CCD CIRCUIT DESCRIPTION1. IC ConfigurationThe CCD peripheral circuit block basically consists of the fol-lowing ICs.IC911 (RJ23Y3BA1LG) CCD imagerIC901 (MAX8918ITM+T) V driverIC902 (AD9971BCPZRL) CDS, AGC, A/D converter,H driver, vertical TG2. IC911 (CCD)[Structure]1/2.33 inch 12.53 million picture element CCDEffective pixels 4040 (H) X 3032 (V)Pixels in total 4102 (H) X 3057 (V)Optical blackHorizontal (H) direction: Front 2 pixels, Rear 60 pixelsVertical (V) direction: Below 19 pixels, Above 6 pixelsDummy bit number Horizontal : 26 Vertical :633, 36,21, 20,16, 3823, 26, 19,29, 40,39, 2237, 32, 24,25, 18, 17,31, 302, 14, 34V1A, V1B, V7A,V7B, V9A, V9B,V11A, V11BV6, V8, V10,V12,V13A,V13B, V14Vertical shift register clock pulseVertical shift register clock pulseGND-7 V, 0 V, 14.5 V0 VVertical shift register clock pulseGNDV2, V4,V15A, V15B,V15C, V16-7 V, 0 V-7 V, 0 VOSPowerCCD outputSubstrate clock DC 21.0 Vp-pDC Aprox. 7.3 V14.5 VOD9135OFDGNDProtection P wellLH1 End horizontal shift register clock pulseHorizontal shift register clock pulseH1A, H2A,H1B, H2B0 V, 3.3 V6, 7,12, 13428, 27 V3, V5 Vertical shift register clock pulseSubstrate controlOFDC1, 211, 8 0 V, 3.3 V (When importing allpicture element: 3.3 V)-7 V, 0 V, 14.5 VRS Reset pulse3PW15 DC3.3 Vp-p-7 V0 V, 3.3 VDC32 31øV11A252627282930øV11BøV12øV3øV5øV8øV7B33øV234 GND35 OSøV1B36øV43711 12øH1B 151413øH2BGNDPW10NC9OFD8OFDC2OFDC17øH2A6øH1A5NCøV1AøV16 38GND 2øLH1 4øRS 3øV15C16øV9B17øV9A18øV1422øV623øV7A24øV13BøV13A 40OD 1øV15A21øV15B20øV101939Pin 1619602 HVPin 21