United Electronic Industries DNR-AI-207 User Manual
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Contents
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DNx-AI-207 Analog Input BoardChapter 3 22Programming with the Low-Level APIDecember 2017 www.ueidaq.com508.921.4600© Copyright 2017United Electronic Industries, Inc.3.6 ConfiguringChannels &Scan Rate inACB ModeIn ACB mode, the channel list (cl) array is configured the same way asdescribed in Section 3.4.1 with some additional configuration. The cl is passedto chassis firmware via the DqAcbInitOps() function, along with otherparameters including an additional Config parameter and the sample rate.The Config parameter is built with the following flags:// 207 unit configuration word#define CFG207 (DQ_LN_ENABLED \|DQ_LN_ACTIVE \|DQ_LN_IRQEN \|DQ_LN_CLCKSRC0 \|DQ_LN_STREAMING \|DQ_AI208_MODEFIFO \|DQ_LN_RAW32)uint32 Config = CFG207;• DQ_LN_ENABLE enables all board operations.• DQ_LN_CLCKSRC0 selects the internal channel list clock (cl) source as atime base. To select a clock generated external to the board and routed inover the chassis SYNC bus (for example, a 1PPS-synchronized clock gen-erated on the CPU), select DQ_LN_CLCKSRC1. (Refer to the previous sectionfor more information.)The channel list and other configuration parameters get passed to DqAcbInitOps:DqAcbInitOps(bcb,&Config,0, //TrigSizeNULL, //pDQSETTRIG TrigMode&fCLClk,0, //float* fCVClk, not using on this board&CHAN_LIST_SZ,cl,0,&acb);where• bcb points to the buffer control block: each new advanced circular buf-fer will have a BCB structure allocated to it• fCLKClk is a float set to the sample rate• CHAN_LIST_SZ is the number of channels (including timestamp) thatyou are programming• cl is the array of channel configuration• acb is a structure of type DQACBCFG that configures ACB parameters.See Table 3-2.Refer to the PowerDNA API Reference Manual for a full list of flags anddescriptions of ACB API and parameters. |
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