Yaesu FT-250R Technical Supplement

Also see for FT-250R: Manual Operating manual

Contents

Yaesu FT-250R Technical Supplement Manual pdf 8 page image

8 FT-250R Technical SupplementCircuit DescriptionTransmit Signal PathSpeech input from the microphone is amplified by Q1064(NJM2902V), then filtered and sent to any installed op-tional signaling unit. The audio which returns from theoptional unit then is passed to the pre-emphasis network.The processed audio may then be mixed with a CTCSS tonegenerated by the microprocessor Q1035 (M3826AEFGP);it is then delivered to D1010 (HSC277) for frequency mod-ulation of the PLL carrier (up to ±5kHz from the unmod-ulated carrier) at the transmitting frequency.If an external microphone is used, PTT switching is con-trolled by Q1054 (UMZ2N), which signals the micropro-cessor Q1035 when the impedance at the microphone jackdrops.If a CDCSS code is enabled for transmission, the code isgenerated by microprocessor Q1035 and delivered toD1015 (HVC350B) for CDCSS modulating.If DTMF is enabled for transmission, the tone is generat-ed by the microprocessor Q1035 and applied to the splat-ter filter section in place of the speech audio. Also, thetone is amplified for monitoring in the loudspeaker.The modulated signal from the VCO Q1023 (2SC5374) isbuffered by Q1022 and Q1018 (both 2SC5374). The low-level transmit signal is amplified by Q1010 (2SC5226-5)and Q1009 (2SK3074); it is then applied to the final am-plifier Q1008 (RD07MVS1A), which provides up to 5watts output power.The transmit signal then passes through the antennaswitch D1001 (RLS135) and is low-pass filtered to sup-press harmonic spurious radiation before delivery to theantenna.Automatic Transmit Power ControlDrain current of the final amplifier Q1008 (RD07MVS1A)is sampled by R1028 and R1035. The resulting DC is fedback through the APC amplifier Q1003 (NJM2904V) tothe driver amplifier Q1009 (2SK3074) and final amplifi-er Q1008, for control of the power output.The microprocessor selects either “High” or “Low” pow-er levels.Transmit InhibitWhen the PLL is unlocked, pin 7 of PLL subsystem ICQ1030 (MB15A01PFV1) goes to a logic “Low.” The re-sulting DC unlock control voltage is passed through theinversion amplifier Q1032 (2SA1774) to pin 8 of the mi-croprocessor Q1035. While the PLL is unlocked, pin 15 ofQ1035 remains “Low,” disabling the gate voltages of driv-er amplifier Q1009 (2SK3074) and final amplifier Q1008(RD07MVS1A), thereby disabling the transmitter.Spurious SuppressionGeneration of spurious products by the transmitter isminimized by the fundamental carrier frequency beingequal to final transmitting frequency, modulated directlyin the transmit VCO. Additional harmonic suppression isprovided by a low-pass filter consisting of coils L1001,L1002, L1003, L1006, L1007 & L1008 and capacitors C1001,C1002, C1003, C1004, C1006, C1007, C1019, C1020, C1021& C1022, resulting in more than 60 dB of harmonic sup-pression prior to delivery to the antenna.PLL Frequency SynthesizerThe PLL circuitry on the Main Unit consists of VCO Q1023(2SC5374), VCO buffers Q1022 and Q1019 (both2 S C 5 3 7 4 ) , a n d P L L s u b s y s t e m I C Q 1 0 3 0(MB15A01PFV1), which contains a reference divider, se-rial-to-parallel data latch, programmable divider, phasecomparator, and charge pump.Stability is maintained by a regulated 3.3 V supply pro-vided via Q1051 (S-812C33AUA) and 21.25 MHz refer-ence frequency crystal X1001, as well as the reference os-cillator’s temperature compensating thermistor and ca-pacitors.While receiving, VCO Q1023 oscillates between 122.3 and126.3 MHz according to the transceiver version and theprogrammed receiving frequency. The VCO output isbuffered by Q1022 and Q1019, then applied to the pres-caler section of Q1030. There the VCO signal is dividedby 64 or 65, according to a control signal from the datalatch section of Q1030, before being sent to the program-mable divider section of Q1030.The data latch section of Q1030 also receives serial divid-ing data from the microprocessor, Q1035, which causesthe pre-divided VCO signal to be further divided in theprogrammable divider section, depending upon the de-sired receive frequency, so as to produce a 5 kHz or 6.25kHz derivative of the current VCO frequency.Meanwhile, the reference divider section of Q1030 dividesthe 21.25 MHz crystal reference X1001, by 4250 (or 3400)to produce the 5 kHz (or 6.25 kHz) loop reference (respec-tively).The 5 kHz (or 6.25 kHz) signal from the programmabledivider (derived from the VCO) and that derived fromthe reference oscillator are applied to the phase detectorsection of Q1030, which produces a pulsed output withpulse duration depending on the phase difference betweenthe input signals.