Yamaha RX-V365 Service Manual

Also see for HTR-6230: Owner's manual Owner's manual Owner's manual Connection guide Owner's manual

Contents

51RX-V365/HTR-6230RX-V365/HTR-6230Pin No. Function Name I/O Detail of Function41 ROUT3 O DAC3 R ch analog output pin42 NC – No connect pinNo internal bonding / This pin should be opened43 LOUT2 O DAC2 L ch analog output pin44 NC – No connect pinNo internal bonding / This pin should be opened45 ROUT2 O DAC2 R ch analog output pin46 NC – No connect pinNo internal bonding / This pin should be opened47 LOUT1 O DAC1 L ch analog output pin48 NC – No connect pinNo internal bonding / This pin should be opened49 ROUT1 O DAC1 R ch analog output pin50 NC – No connect pinNo internal bonding / This pin should be opened51 LIN I L ch analog input pin52 RIN I R ch analog input pin53 VCOM – Common voltage output pin2.2 F capacitor should be connected to AVSS externally54 VREFH – Positive voltage reference input pin, AVDD55 AVDD – Analog power supply pin, 4.5 V to 4.5 V56 AVSS – Analog ground pin, 0 V57 RX0 I Receiver channel 0 pin (Internal biased pin / Internally biased at PVDD/2)58 NC – No connect pinNo internal bonding / This pin should be connected to PVSS59 RX1 I Receiver channel 1 pin (Internal biased pin / Internally biased at PVDD/2)60 TEST1 I Test 1 pinThis pin should be connected to PVSS61 RX2 I Receiver channel 2 pin (Internal biased pin / Internally biased at PVDD/2)62 NC – No connect pinNo internal bonding / This pin should be connected to PVSS63 RX3 I Receiver channel 3 pin (Internal biased pin / Internally biased at PVDD/2)64 PVSS – PLL ground pin65 R – External resistor pin12 k-ohms +/-1 % resistor should be connected to PVSS externally66 PVDD – PLL power supply pin, 4.5 V to 4.5 V67 RX4 I Receiver channel 4 pin (Internal biased pin / Internally biased at PVDD/2)68 TEST2 I Test 2 pinThis pin should be connected to PVSS69 RX5 I Receiver channel 5 pin (Internal biased pin / Internally biased at PVDD/2)70 CAD0 I Chip address 0 pin (ADC/DAC part)71 RX6 I Receiver channel 6 pin (Internal biased pin / Internally biased at PVDD/2)72 CAD1 I Chip address 1 pin (ADC/DAC part)73 RX7 I Receiver channel 7 pin (Internal biased pin / Internally biased at PVDD/2)74 I2C I Control mode select pin“L”: 4-wire serial, “H”: I2C bus75 DAUX2 I Auxiliary audio data input pin (DIR/DIT part)76 VIN I V-bit input pin for transmitter output77 MCLK I Master clock input pin78 TX0 O Transmit channel (through data) output 0 pin79 TX1 OTransmit channel output 1 pinWhen TX bit = “0”, transmit channel (through data) output 1 pin.When TX bit = “1”, transmit channel (DAUX2 data) output pin (default)80 INT0 O Interrupt 0 pinNote: All input pins except internal biased pins and internal pull-down pin should not be left floating.