No. Function Name(P.C.B.) TYPE(1) PULL(2) GPIO(3) Detail of Function1 VSS2 AHCLKX0/AHCLKX2 IO – Y McASP0 and McASP2 transmit master clock3 AMUTE0 IO – Y McASP0 mute output4 AMUTE1 IO – Y McASP1 mute output5 AHCLKX1 IO – Y McASP1 transmit master clock6 VSS7 ACLKX1 IO – Y McASP1 transmit bit clock8 CVDD9 ACLKR1 IO – Y McASP1 receive bit clock10 DVDD11 AFSX1 IO – Y McASP1 transmit frame Sync (L/R clock)12 AFSR1 IO – Y McASP1 receive frame Sync (L/R clock)13 VSS14 RESET IO – N Device reset pin15 VSS16 CVDD17 CLKIN IO – N Alternate clock input (3.3-V LVCMOS input)18 VSS19 TMS IO IPU N Test mode select20 CVDD21 TRST IO IPU N Test reset22 OSCVSS PWR – N Oscillator Vss tap point (for filter only)23 OSCIN IO – N 1.2-V oscillator input24 NC O – N25 OSCVDD PWR – N Oscillator 1.2-V Vpp tap point (for filter only)26 VSS27 PLLHV PWR – N PLL 3.3-V supply input (requires external filter)28 TDI IO IPU N Test data in29 TDO OZ IPU N Test data out30 VSS31 DVDD32 EMU[0] IO IPU N Emulation pin 033 CVDD34 EMU[1] IO IPU N Emulation pin 135 TCK IO IPU N Test clock36 Ground(Vss)37 EM_CAS O – N SDRAM column address strobe38 EM_WE O – N SDRAM write enable39 EM_WE_DQM[0] O – N Write enable or byte enable for EM_D [7:0]40 VSS41 EM_D[7] IO – N EMIF data bus [lower 16-bits]42 DVDD43 EM_D[6] IO – N EMIF data bus [lower 16-bits]44 CVDD45 EM_D[5] IO – N EMIF data bus [lower 16-bits]46 EM_D[4] IO – N EMIF data bus [lower 16-bits]47 VSS48 EM_D[3] IO – N EMIF data bus [lower 16-bits]49 EM_D[2] IO – N EMIF data bus [lower 16-bits]50 DVDD53HTR-2064/NS-B20/NS-C20/NS-SWP20HTR-2064/NS-B20/NS-C20/NS-SWP20