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LAPIS Semiconductor ML62Q1725 manuals

ML62Q1725 first page preview

ML62Q1725

Brand: LAPIS Semiconductor | Category: Microcontrollers
Table of contents
  1. FEUL62Q1000
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Features
  17. BLOCK DIAGRAM
  18. Pin Layout
  19. PIN LIST
  20. PIN DESCRIPTION
  21. TERMINATION OF UNUSED PINS
  22. General Description
  24. Wait mode and No-wait mode
  25. Coprocessor
  26. List of Coprocessor General-purpose Registers
  27. How to Use Multiplier/Divider
  28. Memory Space
  29. Configuration
  30. Data Memory Space
  31. Description of Registers
  32. Data Segment Register (DSR)
  33. Flash Remap Address Register (REMAPADD)
  34. Remapping Function
  35. Description of Remapping Function
  36. Code Option Remap
  37. Reset Function
  39. Reset Status Register (RSTAT)
  40. Safety Function Reset Status Register (SRSTAT)
  41. Description of Operation
  42. System Reset Mode
  43. Power-On Reset
  48. Stop Code Acceptor (STPACP)
  49. Standby Control Register (SBYCON)
  50. Software Reset Acceptor (SOFTRACP)
  51. Software Reset Control Register (SOFTRCON)
  52. Block Clock Control Register 0 (BCKCON0)
  53. Block Clock Control Register 1 (BCKCON1)
  54. Block Clock Control Register 2 (BCKCON2)
  55. Block Clock Control Register 3 (BCKCON3)
  56. Block Reset Control Register 0 (BRECON0)
  57. Block Reset Control Register 1 (BRECON1)
  58. Block Reset Control Register 2 (BRECON2)
  59. Block Reset Control Register 3 (BRECON3)
  61. HALT-H mode
  62. STOP mode
  63. STOP-D Mode
  64. Operation of Each Function in Standby Mode
  65. Block Control Function
  66. Interrupts
  68. Interrupt Enable Register 01 (IE01)
  69. Interrupt Enable Register 23 (IE23)
  70. Interrupt Enable Register 45 (IE45)
  71. Interrupt Enable Register 67 (IE67)
  72. Interrupt Request Register 01 (IRQ01)
  73. Interrupt Request Register 23 (IRQ23)
  74. Interrupt Request Register 45 (IRQ45)
  75. Interrupt Request Register 67 (IRQ67)
  76. Interrupt Level Control Enable Register (ILEN)
  77. Current Interrupt Level Management Register (CIL)
  78. Interrupt Level Control Register 0 (ILC0)
  79. Interrupt Level Control Register 1 (ILC1)
  80. Interrupt Level Control Register 2 (ILC2)
  81. Interrupt Level Control Register 3 (ILC3)
  82. Interrupt Level Control Register 4 (ILC4)
  83. Interrupt Level Control Register 5 (ILC5)
  84. Interrupt Level Control Register 6 (ILC6)
  85. Interrupt Level Control Register 7 (ILC7)
  87. Maskable Interrupt Processing
  88. Notes on Interrupt Routine (with Interrupt Level Control Disabled)
  89. Flow Charts When Interrupt Level Control Is Enabled
  90. How To Write Interrupt Processing When Interrupt Level Control Enabled
  91. Interrupt Disable State
  92. Clock Generation Circuit
  94. List of Pins
  96. High-Speed Clock Mode Register (FHCKMOD)
  97. Low-speed Clock Mode Register (FLMOD)
  98. Clock Control Register (FCON)
  99. High-Speed Clock Wake-up Time Setting Register (FHWUPT)
  100. Backup Control Register (FBUCON)
  101. Backup Clock Status Register (FBUSTAT)
  102. Clock Backup Test Mode Acceptor (FBTACP)
  103. Clock Backup Test Mode (FBTCON)
  104. Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ)
  106. High-Speed Clock
  107. WDT Clock
  108. Switching of System Clock
  109. Switching Low-speed Clock
  110. Low Speed Time Base Counter
  114. Low Speed Time Base Counter Register (LTBR)
  115. Low Speed Time Base Register Control Register (LTBCCON)
  116. Simplified RTC Time Base Counter Register (LTBRR)
  117. Low Speed Time Base Counter frequency adjustment Register (LTBADJ)
  118. Low Speed Time Base Counter Interrupt Selection Register (LTBINT)
  120. Low Speed Time Base Counter Frequency Adjustment Function
  121. The way of monitoring the frequency on LCD drive outputs
  126. Bit Timer n Data Register (TMHnD: n = 0 to 7)
  127. Bit Timer n Counter Register (TMHnC: n = 0 to 7)
  128. Bit Timer n Mode Register (TMHnMOD: n = 0 to 7)
  129. Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7)
  130. Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7)
  131. Bit Timer Start Register (TMHSTR)
  132. Bit Timer Stop Register (TMHSTP)
  133. Bit Timer Status Register (TMHSTAT)
  135. Bit Timer Mode
  136. Common Operation
  137. Functional Timer
  140. List of Pin
  142. FTMn Cycle Register (FTnP: n = 0 to 7)
  143. FTMn Event Register A (FTnEA: n = 0 to 7)
  144. FTMn Event Register B (FTnEB: n = 0 to 7)
  145. FTMn Dead Time Register (FTnDT: n = 0 to 7)
  146. FTMn Counter Register (FTnC: n = 0 to 7)
  147. FTMn Status Register (FTnSTAT: n = 0 to 7)
  148. FTMn Mode Register (FTnMOD: n = 0 to 7)
  149. FTMn Clock Register (FTnCLK: n= 0 to 7)
  150. FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7)
  151. FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7)
  152. FTMn Interrupt Enable Register (FTnINTE: n = 0 to 7)
  153. FTMn Interrupt Status Register (FTnINTS: n = 0 to 7)
  154. FTMn Interrupt Clear Register (FTnINTC: n = 0 to 7)
  155. FTM Common Update Register (FTCUD)
  156. FTM Common Control Register (FTCCON)
  157. FTM Common Start Register (FTCSTR)
  158. FTM Common Stop Register (FTCSTP)
  159. FTM Common Status Register (FTCSTAT)
  161. Counter Operation (Common to All Modes)
  162. TIMER Mode Operation
  163. CAPTURE Mode Operation
  164. PWM1 Mode Operation
  165. PWM2 Mode Operation
  166. Event Trigger/Emergency Stop Trigger Control
  167. Output at Counter Stop
  168. Changing Cycle, Event A/B, and Dead Time during Operation
  169. Interrupt Source
  170. Watchdog Timer
  174. Watchdog Timer Control Register (WDTCON)
  175. Watchdog Timer Mode Register (WDTMOD)
  176. Watchdog Timer Counter Register (WDTMC)
  177. Watchdog Status Register (WDTSTA)
  179. How to Clear WDT Counter
  180. Window Function Disabled Mode
  181. Window Function Enabled Mode
  182. Serial Communication Unit
  186. Combination of SSIO port
  188. Serial Communication Unit n Transmit/Receive Buffer (SDnBUF)
  189. Serial Communication Unit n Mode Register (SUnMOD)
  190. Serial Communication Unit n Transmission Interval Setting Register (SUnDLY)
  191. Serial Communication Unit n Control Register (SUnCON)
  192. Synchronous Serial Port n Mode Register (SIOnMOD)
  193. Synchronous Serial Port n Status Register (SIOnSTAT)
  194. UARTn0 Mode Register (UAn0MOD)
  195. UARTn1 Mode Register (UAn1MOD)
  196. UARTn0 Baud Rate Register (UAn0BRT)
  197. UARTn0 Baud Rate Adjustment Register (UAn0BRC)
  198. UARTn0 Status Register (UAn0STAT)
  199. UARTn1 Status Register (UAn1STAT)
  201. Asynchronous Serial Interface (UART)
  202. I2C Bus Unit
  207. Master Mode Communication Operation Timing
  208. Slave Operation
  209. Slave Mode Communication Operation Timing
  210. Operation Waveforms
  211. I2C Master
  216. Communication Operation Timing
  218. DMA Controller
  222. DMA Channel n Transfer Mode Register (DCnMOD: n = 0, 1)
  223. DMA Channel n Transfer Count Register (DCnTN: n = 0, 1)
  224. DMA Channel n Transfer Source Address Register (DCnSA: n = 0, 1)
  225. DMA Channel n Transfer Destination Address Register (DCnDA: n = 0, 1)
  226. DMA Transfer Enable Register (DCEN)
  227. DMA Status Register (DSTAT)
  228. DMA Interrupt Status Clear Register (DICLR)
  230. DMA transfer Operation Timing Diagram
  231. UART Continuous Transmission Using DMA Transfer
  232. UART Continuous Reception Using DMA Transfer
  233. DMA Transfer Target Block
  234. Buzzer
  239. Buzzer 0 Control Register (BZ0CON)
  240. Buzzer 0 Mode Register (BZ0MOD)
  242. Intermittent Sound 2 Mode
  243. Single Sound Mode
  244. Continuous Sound Mode
  246. Simplified RTC 16.1 General Description
  248. Simplified RTC Acceptor (SRTCACP)
  249. Simplified RTC Minute/Second Counter (SRTCMAS)
  250. Simplified RTC Control Register (SRTCCON)
  252. Simplified RTC Setting Example for Writing Time Data
  255. Port n Data Register (PnD:n=0 to 9, A, B)
  256. Port n Mode Register 01 (PnMOD01:n=0 to 9, A, B)
  257. Port n Mode Register 23 (PnMOD23:n=0 to 9, A, B)
  258. Port n Mode Register 45 (PnMOD45:n=0 to 2, 4 to 9, A, B)
  259. Port n Mode Register 67 (PnMOD67:n=0 to 2, 4 to 9, A, B)
  260. Port n Pulse Mode Register (PnPMD:n=0 to 3)
  261. Port n Pulse Selection Register (PnPSL:n=0 to 3)
  262. PORTXT data input register (PXTDI)
  263. PORTXT mode register 01 (PXTMOD01)
  265. Carrier Frequency Output
  266. Port Output Level Test
  267. Notes for using the P00/TEST0 pin
  268. External Interrupt Function
  274. External Interrupt Control Register 0 (EICON0)
  275. External Interrupt Mode Register 0 (EIMOD0)
  276. Expanded External Interrupt Control Register 0 (EEICON0)
  277. Expanded External Interrupt Mode Register 0 (EEIMOD0)
  278. Expanded External Interrupt Mode Register 1(EEIMOD1)
  279. Expanded External Interrupt Status Register (EEISTAT)
  280. Expanded External Interrupt Clear Register (EEINTC)
  282. External Trigger Signal
  283. External Interrupt Setting Flow
  284. Expanded External Interrupt Setting Flow
  285. CRC (Cycle Redundancy Check) Generator
  289. Automatic CRC Calculation Start Address Setting Register (CRCSAD)
  290. Automatic CRC Calculation End Address Setting Register (CRCEAD)
  291. Automatic CRC Calculation Start Segment Setting Register (CRCSSEG)
  292. Automatic CRC Calculation End Segment Setting Register (CRCESEG)
  293. CRC Data Register (CRCDATA)
  294. CRC Calculation Result Register (CRCRES)
  295. Automatic CRC Mode Register (CRCMOD)
  297. Automatic CRC Calculation Mode
  298. Analog Comparator
  303. Comparator n Control Register (CMPnCON: n=0,1)
  304. Comparator n Mode Register (CMPnMOD: n=0,1)
  306. Interrupt Request
  307. D/A Converter
  312. D/A Converter 0 Control Register (DACCON)
  313. D/A Converter 0 Code Register (DACCODE)
  314. D/A Converter 1 Control Register (DACCON1)
  315. D/A Converter 1 Code Register (DACCODE1)
  321. Voltage Level Supervisor 0 Control Register (VLS0CON)
  322. Voltage Level Supervisor 0 Mode Register (VLS0MOD)
  323. Voltage Level Supervisor 0 Level Register (VLS0LV)
  324. Voltage Level Supervisor 0 Sampling Register (VLS0SMP)
  326. Supervisor Mode
  327. Single Mode
  328. Successive Approximation Type A/D Converter
  333. SA-ADC Result Register n (SADRn : n=0 to 15, 16)
  334. SA-ADC Result Register (SADR)
  335. SA-ADC Upper/Lower Limit Status Register 0 (SADULS0)
  336. SA-ADC Upper/Lower Limit Status Register 1 (SADULS1)
  337. SA-ADC Mode Register (SADMOD)
  338. SA-ADC Control Register (SADCON)
  339. SA-ADC Enable Register 0 (SADEN0)
  340. SA-ADC Enable Register 1 (SADEN1)
  341. SA-ADC Conversion Interval Setting Register (SADSTM)
  342. SA-ADC Upper/Lower Limit Mode Register (SADLMOD)
  343. SA-ADC Upper Limit Setting Register (SADUPL)
  344. SA-ADC Reference Voltage Control Register (VREFCON)
  345. SA-ADC Interrupt Mode Register (SADIMOD)
  346. SA-ADC Trigger Register (SADTRG)
  347. SA-ADC test mode register (SADTMOD)
  349. How to test the Successive Approximation Type A/D Converter
  350. A/D Conversion Time Setting
  351. Notes on SA-ADC
  352. Noise Suppression
  355. Flash Memory
  358. Flash Address Register (FLASHA)
  359. Flash Segment Register (FLASHSEG)
  360. Flash Data Register 0 (FLASHD0)
  361. Flash Data Register 1 (FLASHD1)
  362. Flash Control Register (FLASHCON)
  363. Flash Acceptor (FLASHACP)
  364. Flash Self Register (FLASHSLF)
  365. Flash Status Register (FLASHSTA)
  366. Self-programming
  367. Programming program memory space
  368. Programming data flash area
  369. Notes on use of self-programming
  370. In-System Programming Function
  371. Communication command
  372. Transition Command to ISP Mode
  373. Flash Memory Handling
  374. Code Option
  375. Description of Code Option
  376. Code Options 1 (CODEOP1)
  377. Code Options 2 (CODEOP2)
  378. Code Option Data Setting
  379. LCD Driver
  380. Configuration of LCD Display Function
  381. Configuration of Bias Generation Circuit
  384. Bias Control Register(BIASCON)
  385. Display Mode Register(DSPMOD)
  386. Display Control Register(DSPCON)
  387. Segment Mode Register0 (SEGMOD0)
  388. Segment Mode Register1 (SEGMOD1)
  389. Segment Mode Register2 (SEGMOD2)
  390. Segment Mode Register3 (SEGMOD3)
  391. Segment Mode Register4 (SEGMOD4)
  392. Display Register(DSPR00 to DSPR64)
  394. Common Output Waveform
  395. Segment Output Waveform
  396. Common Output Waveform for LED drive
  397. Segment Output Waveform for LED drive
  398. On-Chip Debug Function
  402. How to Use On-chip Debug Function
  403. Operation of Peripheral Circuits during breaks in the on-chip debug mode
  404. Safety Function
  407. RAM Guard Setting Register (RAMGD)
  408. SFR Guard Setting Register 0 (SFRGD0)
  409. SFR Guard Setting Register 1 (SFRGD1)
  410. RAM Parity Setting Register (RASFMOD)
  411. Communication Test Setting Register (COMFT0)
  412. MCU Status Interrupt Enable Register (MCINTEL)
  413. MCU Status Interrupt Register (MCISTATL)
  414. MCU Status Interrupt Clear Register (MCINTCL)
  416. Unused ROM Area Access Reset Function
  417. Clock Mutual Monitoring Function
  418. CRC Calculation
  419. Appendix A Register List
  420. Appendix B Package Dimensions
  421. Appendix C Instruction Execution Cycle
  422. Appendix D Application Circuit Example
  423. Revision History
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