Contents - FEUL62Q1000
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Features
- BLOCK DIAGRAM
- Pin Layout
- PIN LIST
- PIN DESCRIPTION
- TERMINATION OF UNUSED PINS
- General Description
- Wait mode and No-wait mode
- Coprocessor
- List of Coprocessor General-purpose Registers
- How to Use Multiplier/Divider
- Memory Space
- Configuration
- Data Memory Space
- Description of Registers
- Data Segment Register (DSR)
- Flash Remap Address Register (REMAPADD)
- Remapping Function
- Description of Remapping Function
- Code Option Remap
- Reset Function
- Reset Status Register (RSTAT)
- Safety Function Reset Status Register (SRSTAT)
- Description of Operation
- System Reset Mode
- Power-On Reset
- Stop Code Acceptor (STPACP)
- Standby Control Register (SBYCON)
- Software Reset Acceptor (SOFTRACP)
- Software Reset Control Register (SOFTRCON)
- Block Clock Control Register 0 (BCKCON0)
- Block Clock Control Register 1 (BCKCON1)
- Block Clock Control Register 2 (BCKCON2)
- Block Clock Control Register 3 (BCKCON3)
- Block Reset Control Register 0 (BRECON0)
- Block Reset Control Register 1 (BRECON1)
- Block Reset Control Register 2 (BRECON2)
- Block Reset Control Register 3 (BRECON3)
- HALT-H mode
- STOP mode
- STOP-D Mode
- Operation of Each Function in Standby Mode
- Block Control Function
- Interrupts
- Interrupt Enable Register 01 (IE01)
- Interrupt Enable Register 23 (IE23)
- Interrupt Enable Register 45 (IE45)
- Interrupt Enable Register 67 (IE67)
- Interrupt Request Register 01 (IRQ01)
- Interrupt Request Register 23 (IRQ23)
- Interrupt Request Register 45 (IRQ45)
- Interrupt Request Register 67 (IRQ67)
- Interrupt Level Control Enable Register (ILEN)
- Current Interrupt Level Management Register (CIL)
- Interrupt Level Control Register 0 (ILC0)
- Interrupt Level Control Register 1 (ILC1)
- Interrupt Level Control Register 2 (ILC2)
- Interrupt Level Control Register 3 (ILC3)
- Interrupt Level Control Register 4 (ILC4)
- Interrupt Level Control Register 5 (ILC5)
- Interrupt Level Control Register 6 (ILC6)
- Interrupt Level Control Register 7 (ILC7)
- Maskable Interrupt Processing
- Notes on Interrupt Routine (with Interrupt Level Control Disabled)
- Flow Charts When Interrupt Level Control Is Enabled
- How To Write Interrupt Processing When Interrupt Level Control Enabled
- Interrupt Disable State
- Clock Generation Circuit
- List of Pins
- High-Speed Clock Mode Register (FHCKMOD)
- Low-speed Clock Mode Register (FLMOD)
- Clock Control Register (FCON)
- High-Speed Clock Wake-up Time Setting Register (FHWUPT)
- Backup Control Register (FBUCON)
- Backup Clock Status Register (FBUSTAT)
- Clock Backup Test Mode Acceptor (FBTACP)
- Clock Backup Test Mode (FBTCON)
- Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ)
- High-Speed Clock
- WDT Clock
- Switching of System Clock
- Switching Low-speed Clock
- Low Speed Time Base Counter
- Low Speed Time Base Counter Register (LTBR)
- Low Speed Time Base Register Control Register (LTBCCON)
- Simplified RTC Time Base Counter Register (LTBRR)
- Low Speed Time Base Counter frequency adjustment Register (LTBADJ)
- Low Speed Time Base Counter Interrupt Selection Register (LTBINT)
- Low Speed Time Base Counter Frequency Adjustment Function
- The way of monitoring the frequency on LCD drive outputs
- Bit Timer n Data Register (TMHnD: n = 0 to 7)
- Bit Timer n Counter Register (TMHnC: n = 0 to 7)
- Bit Timer n Mode Register (TMHnMOD: n = 0 to 7)
- Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7)
- Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7)
- Bit Timer Start Register (TMHSTR)
- Bit Timer Stop Register (TMHSTP)
- Bit Timer Status Register (TMHSTAT)
- Bit Timer Mode
- Common Operation
- Functional Timer
- List of Pin
- FTMn Cycle Register (FTnP: n = 0 to 7)
- FTMn Event Register A (FTnEA: n = 0 to 7)
- FTMn Event Register B (FTnEB: n = 0 to 7)
- FTMn Dead Time Register (FTnDT: n = 0 to 7)
- FTMn Counter Register (FTnC: n = 0 to 7)
- FTMn Status Register (FTnSTAT: n = 0 to 7)
- FTMn Mode Register (FTnMOD: n = 0 to 7)
- FTMn Clock Register (FTnCLK: n= 0 to 7)
- FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7)
- FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7)
- FTMn Interrupt Enable Register (FTnINTE: n = 0 to 7)
- FTMn Interrupt Status Register (FTnINTS: n = 0 to 7)
- FTMn Interrupt Clear Register (FTnINTC: n = 0 to 7)
- FTM Common Update Register (FTCUD)
- FTM Common Control Register (FTCCON)
- FTM Common Start Register (FTCSTR)
- FTM Common Stop Register (FTCSTP)
- FTM Common Status Register (FTCSTAT)
- Counter Operation (Common to All Modes)
- TIMER Mode Operation
- CAPTURE Mode Operation
- PWM1 Mode Operation
- PWM2 Mode Operation
- Event Trigger/Emergency Stop Trigger Control
- Output at Counter Stop
- Changing Cycle, Event A/B, and Dead Time during Operation
- Interrupt Source
- Watchdog Timer
- Watchdog Timer Control Register (WDTCON)
- Watchdog Timer Mode Register (WDTMOD)
- Watchdog Timer Counter Register (WDTMC)
- Watchdog Status Register (WDTSTA)
- How to Clear WDT Counter
- Window Function Disabled Mode
- Window Function Enabled Mode
- Serial Communication Unit
- Combination of SSIO port
- Serial Communication Unit n Transmit/Receive Buffer (SDnBUF)
- Serial Communication Unit n Mode Register (SUnMOD)
- Serial Communication Unit n Transmission Interval Setting Register (SUnDLY)
- Serial Communication Unit n Control Register (SUnCON)
- Synchronous Serial Port n Mode Register (SIOnMOD)
- Synchronous Serial Port n Status Register (SIOnSTAT)
- UARTn0 Mode Register (UAn0MOD)
- UARTn1 Mode Register (UAn1MOD)
- UARTn0 Baud Rate Register (UAn0BRT)
- UARTn0 Baud Rate Adjustment Register (UAn0BRC)
- UARTn0 Status Register (UAn0STAT)
- UARTn1 Status Register (UAn1STAT)
- Asynchronous Serial Interface (UART)
- I2C Bus Unit
- Master Mode Communication Operation Timing
- Slave Operation
- Slave Mode Communication Operation Timing
- Operation Waveforms
- I2C Master
- Communication Operation Timing
- DMA Controller
- DMA Channel n Transfer Mode Register (DCnMOD: n = 0, 1)
- DMA Channel n Transfer Count Register (DCnTN: n = 0, 1)
- DMA Channel n Transfer Source Address Register (DCnSA: n = 0, 1)
- DMA Channel n Transfer Destination Address Register (DCnDA: n = 0, 1)
- DMA Transfer Enable Register (DCEN)
- DMA Status Register (DSTAT)
- DMA Interrupt Status Clear Register (DICLR)
- DMA transfer Operation Timing Diagram
- UART Continuous Transmission Using DMA Transfer
- UART Continuous Reception Using DMA Transfer
- DMA Transfer Target Block
- Buzzer
- Buzzer 0 Control Register (BZ0CON)
- Buzzer 0 Mode Register (BZ0MOD)
- Intermittent Sound 2 Mode
- Single Sound Mode
- Continuous Sound Mode
- Simplified RTC 16.1 General Description
- Simplified RTC Acceptor (SRTCACP)
- Simplified RTC Minute/Second Counter (SRTCMAS)
- Simplified RTC Control Register (SRTCCON)
- Simplified RTC Setting Example for Writing Time Data
- Port n Data Register (PnD:n=0 to 9, A, B)
- Port n Mode Register 01 (PnMOD01:n=0 to 9, A, B)
- Port n Mode Register 23 (PnMOD23:n=0 to 9, A, B)
- Port n Mode Register 45 (PnMOD45:n=0 to 2, 4 to 9, A, B)
- Port n Mode Register 67 (PnMOD67:n=0 to 2, 4 to 9, A, B)
- Port n Pulse Mode Register (PnPMD:n=0 to 3)
- Port n Pulse Selection Register (PnPSL:n=0 to 3)
- PORTXT data input register (PXTDI)
- PORTXT mode register 01 (PXTMOD01)
- Carrier Frequency Output
- Port Output Level Test
- Notes for using the P00/TEST0 pin
- External Interrupt Function
- External Interrupt Control Register 0 (EICON0)
- External Interrupt Mode Register 0 (EIMOD0)
- Expanded External Interrupt Control Register 0 (EEICON0)
- Expanded External Interrupt Mode Register 0 (EEIMOD0)
- Expanded External Interrupt Mode Register 1(EEIMOD1)
- Expanded External Interrupt Status Register (EEISTAT)
- Expanded External Interrupt Clear Register (EEINTC)
- External Trigger Signal
- External Interrupt Setting Flow
- Expanded External Interrupt Setting Flow
- CRC (Cycle Redundancy Check) Generator
- Automatic CRC Calculation Start Address Setting Register (CRCSAD)
- Automatic CRC Calculation End Address Setting Register (CRCEAD)
- Automatic CRC Calculation Start Segment Setting Register (CRCSSEG)
- Automatic CRC Calculation End Segment Setting Register (CRCESEG)
- CRC Data Register (CRCDATA)
- CRC Calculation Result Register (CRCRES)
- Automatic CRC Mode Register (CRCMOD)
- Automatic CRC Calculation Mode
- Analog Comparator
- Comparator n Control Register (CMPnCON: n=0,1)
- Comparator n Mode Register (CMPnMOD: n=0,1)
- Interrupt Request
- D/A Converter
- D/A Converter 0 Control Register (DACCON)
- D/A Converter 0 Code Register (DACCODE)
- D/A Converter 1 Control Register (DACCON1)
- D/A Converter 1 Code Register (DACCODE1)
- Voltage Level Supervisor 0 Control Register (VLS0CON)
- Voltage Level Supervisor 0 Mode Register (VLS0MOD)
- Voltage Level Supervisor 0 Level Register (VLS0LV)
- Voltage Level Supervisor 0 Sampling Register (VLS0SMP)
- Supervisor Mode
- Single Mode
- Successive Approximation Type A/D Converter
- SA-ADC Result Register n (SADRn : n=0 to 15, 16)
- SA-ADC Result Register (SADR)
- SA-ADC Upper/Lower Limit Status Register 0 (SADULS0)
- SA-ADC Upper/Lower Limit Status Register 1 (SADULS1)
- SA-ADC Mode Register (SADMOD)
- SA-ADC Control Register (SADCON)
- SA-ADC Enable Register 0 (SADEN0)
- SA-ADC Enable Register 1 (SADEN1)
- SA-ADC Conversion Interval Setting Register (SADSTM)
- SA-ADC Upper/Lower Limit Mode Register (SADLMOD)
- SA-ADC Upper Limit Setting Register (SADUPL)
- SA-ADC Reference Voltage Control Register (VREFCON)
- SA-ADC Interrupt Mode Register (SADIMOD)
- SA-ADC Trigger Register (SADTRG)
- SA-ADC test mode register (SADTMOD)
- How to test the Successive Approximation Type A/D Converter
- A/D Conversion Time Setting
- Notes on SA-ADC
- Noise Suppression
- Flash Memory
- Flash Address Register (FLASHA)
- Flash Segment Register (FLASHSEG)
- Flash Data Register 0 (FLASHD0)
- Flash Data Register 1 (FLASHD1)
- Flash Control Register (FLASHCON)
- Flash Acceptor (FLASHACP)
- Flash Self Register (FLASHSLF)
- Flash Status Register (FLASHSTA)
- Self-programming
- Programming program memory space
- Programming data flash area
- Notes on use of self-programming
- In-System Programming Function
- Communication command
- Transition Command to ISP Mode
- Flash Memory Handling
- Code Option
- Description of Code Option
- Code Options 1 (CODEOP1)
- Code Options 2 (CODEOP2)
- Code Option Data Setting
- LCD Driver
- Configuration of LCD Display Function
- Configuration of Bias Generation Circuit
- Bias Control Register(BIASCON)
- Display Mode Register(DSPMOD)
- Display Control Register(DSPCON)
- Segment Mode Register0 (SEGMOD0)
- Segment Mode Register1 (SEGMOD1)
- Segment Mode Register2 (SEGMOD2)
- Segment Mode Register3 (SEGMOD3)
- Segment Mode Register4 (SEGMOD4)
- Display Register(DSPR00 to DSPR64)
- Common Output Waveform
- Segment Output Waveform
- Common Output Waveform for LED drive
- Segment Output Waveform for LED drive
- On-Chip Debug Function
- How to Use On-chip Debug Function
- Operation of Peripheral Circuits during breaks in the on-chip debug mode
- Safety Function
- RAM Guard Setting Register (RAMGD)
- SFR Guard Setting Register 0 (SFRGD0)
- SFR Guard Setting Register 1 (SFRGD1)
- RAM Parity Setting Register (RASFMOD)
- Communication Test Setting Register (COMFT0)
- MCU Status Interrupt Enable Register (MCINTEL)
- MCU Status Interrupt Register (MCISTATL)
- MCU Status Interrupt Clear Register (MCINTCL)
- Unused ROM Area Access Reset Function
- Clock Mutual Monitoring Function
- CRC Calculation
- Appendix A Register List
- Appendix B Package Dimensions
- Appendix C Instruction Execution Cycle
- Appendix D Application Circuit Example
- Revision History
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ML62Q1000 Series User's ManualContentsFEUL62Q1000 Contents-35.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled)........................................................... 5-415.3.5 Flow Charts When Interrupt Level Control Is Enabled ............................................................................... 5-465.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled .............................................. 5-485.3.7 Interrupt Disable State ................................................................................................................................. 5-51Chapter 66. Clock Generation Circuit ................................................................................................................................ 6-16.1 General Description ....................................................................................................................................... 6-16.1.1 Features .......................................................................................................................................................... 6-16.1.2 Configuration ................................................................................................................................................. 6-26.1.3 List of Pins ..................................................................................................................................................... 6-36.2 Description of Registers................................................................................................................................. 6-46.2.1 List of Registers ............................................................................................................................................. 6-46.2.2 High-Speed Clock Mode Register (FHCKMOD) .......................................................................................... 6-56.2.3 Low-speed Clock Mode Register (FLMOD) ................................................................................................. 6-76.2.4 Clock Control Register (FCON) .................................................................................................................... 6-86.2.5 High-Speed Clock Wake-up Time Setting Register (FHWUPT) .................................................................. 6-96.2.6 Backup Control Register (FBUCON) .......................................................................................................... 6-106.2.7 Backup Clock Status Register (FBUSTAT) ................................................................................................ 6-116.2.8 Clock Backup Test Mode Acceptor (FBTACP) .......................................................................................... 6-126.2.9 Clock Backup Test Mode (FBTCON) ......................................................................................................... 6-136.2.10 Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ) .................................................. 6-146.3 Description of Operation ............................................................................................................................. 6-156.3.1 Low-Speed Clock ........................................................................................................................................ 6-156.3.2 High-Speed Clock ........................................................................................................................................ 6-216.3.3 WDT Clock.................................................................................................................................................. 6-226.3.4 Switching of System Clock.......................................................................................................................... 6-236.3.5 Switching Low-speed Clock ........................................................................................................................ 6-25Chapter 77. Low Speed Time Base Counter ...................................................................................................................... 7-17.1 General Description ....................................................................................................................................... 7-17.1.1 Features .......................................................................................................................................................... 7-17.1.2 Configuration ................................................................................................................................................. 7-27.1.3 List of Pins ..................................................................................................................................................... 7-47.2 Description of Registers................................................................................................................................. 7-57.2.1 List of Registers ............................................................................................................................................. 7-57.2.2 Low Speed Time Base Counter Register (LTBR) ......................................................................................... 7-67.2.3 Low Speed Time Base Register Control Register (LTBCCON) ................................................................... 7-77.2.4 Simplified RTC Time Base Counter Register (LTBRR) ............................................................................... 7-87.2.5 Low Speed Time Base Counter frequency adjustment Register (LTBADJ) .............................................. 7-97.2.6 Low Speed Time Base Counter Interrupt Selection Register (LTBINT) ..................................................... 7-107.3 Description of Operation ............................................................................................................................. 7-127.3.1 Low Speed Time Base Counter Operation .................................................................................................. 7-127.3.2 Low Speed Time Base Counter Frequency Adjustment Function ............................................................... 7-147.3.3 The way of monitoring the frequency on LCD drive outputs ...................................................................... 7-15Chapter 88. 16-Bit Timer ................................................................................................................................................... 8-18.1 General Description ....................................................................................................................................... 8-18.1.1 Features .......................................................................................................................................................... 8-18.1.2 Configuration ................................................................................................................................................ 8-38.1.3 List of Pin ..................................................................................................................................................... 8-48.2 Description of Registers................................................................................................................................. 8-58.2.1 List of Registers ............................................................................................................................................ 8-58.2.2 16-Bit Timer n Data Register (TMHnD: n = 0 to 7) ..................................................................................... 8-78.2.3 16-Bit Timer n Counter Register (TMHnC: n = 0 to 7) ................................................................................ 8-8
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