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MC97F2664
Abov MC97F2664 User Manual
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Abov MC97F2664 User Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Overview
Features
Ordering Information
Development Tools
Figure 1.2 PGMplusUSB (Single Writer)
Block Diagram
Pin Assignment
Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment
Package Diagram
Figure 4.2 64-Pin LQFP-1414 Package
Figure 4.3 64-Pin QFN Package
Figure 4.4 44-Pin MQFP-1010 Package
Pin Description
Port Structures
External Interrupt I/O Port
Electrical Characteristics
A/D Converter Characteristics
Power-On Reset Characteristics
Internal RC Oscillator Characteristics
DC Characteristics
AC Characteristics
SPI Characteristics
UART Characteristics
I2C Characteristics
Data Retention Voltage in Stop Mode
Internal Flash Rom Characteristics
Main Clock Oscillator Characteristics
Sub Clock Oscillator Characteristics
Main Oscillation Stabilization Characteristics
Operating Voltage Range
Recommended Circuit and Layout
Recommended Circuit and Layout with SMPS Power
Typical Characteristics
Figure 7.21 SUB RUN (IDD3) Current
Figure 7.23 STOP (IDD5) Current
Memory
Figure 8.1 Program Memory
Data Memory
Figure 8.3 Lower 128 Bytes RAM
XRAM Memory
Table 8-1 SFR Map Summary
Table 8-2 Extended SFR Map Summary
Table 8-3 SFR Map
Table 8-4 Extended SFR Map
I/O Ports
Table 9-1 Port Register Map
P7 Port
Interrupt Controller
External Interrupt
Interrupt Vector Table
Interrupt Sequence
Effective Timing after Controlling Interrupt Bit
Multi Interrupt
Interrupt Enable Accept Timing
Interrupt Timing
Interrupt Register Description
Peripheral Hardware
Table 11-1 Clock Generator Register Map
Basic Interval Timer
Table 11-2 Basic Interval Timer Register Map
Watch Dog Timer
Figure 11.4 Watch Dog Timer Block Diagram
Watch Timer
Table 11-4 Watch Timer Register Map
Timer 0/1/2/3
Figure 11.6 8-Bit Timer/Counter Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
Figure 11.8 8-Bit PWM Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0/1/2 (Where n = 0, 1, 2, and 3)
Figure 11.10 8-Bit Capture Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
Figure 11.11 Input Capture Mode Operation for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
Figure 11.13 8-Bit Timer 0/1/2/3 Block Diagram (Where n = 0, 1, 2, and 3)
Table 11-6 Timer 0/1/2/3 Register Map
Timer 4/5
Figure 11.14 16-Bit Timer/Counter Mode for Timer 4/5 ( where n= 4 and 5)
Figure 11.16 16-Bit Capture Mode for Timer 4/5 ( where n= 4 and 5)
Figure 11.17 Input Capture Mode Operation for Timer 4/5 ( where n= 4 and 5)
Figure 11.19 16-Bit PPG Mode for Timer 4/5 ( where n= 4 and 5)
Figure 11.20 16-Bit PPG Mode Timming chart for Timer 4/5 ( where n= 4 and 5)
Figure 11.21 16-Bit Timer 4/5 Block Diagram ( where n= 4 and 5)
Timer 6/7/8/9
Figure 11.22 16-Bit Timer/Counter Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
Figure 11.24 16-Bit Capture Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
Figure 11.25 Input Capture Mode Operation for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
Figure 11.27 16-Bit PPG Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
Figure 11.28 16-Bit PPG Mode Timming chart for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
Figure 11.29 16-Bit Timer 6/7/8/9 Block Diagram ( where n= 6,7,8, and 9)
Buzzer Driver
Table 11-12 Buzzer Driver Register Map
SPI 2/3
Figure 11.32 SPI 2/3 Transmit/Receive Timing Diagram at CPHA = 0 (Where n = 2 and 3)
Table 11-13 SPI 2/3 Register Map
UART2/3/4
Figure 11.34 UART Block Diagram(where n = 2,3, and 4)
Figure 11.35 Clock Generation Block Diagram (where n = 2,3, and 4)
Figure 11.36 Frame Format
Figure 11.37 Start Bit Sampling (where n = 2,3, and 4)
Figure 11.39 Stop Bit Sampling and Next Start Bit Sampling (where n = 2,3, and 4)
Table 11-16 Examples of UARTnBD Settings for Commonly Used Oscillator Frequencies
USI0/1 (UART + SPI + I2C)
Figure 11.40 USI0/1 UART Block Diagram (Where n = 0 and 1)
Figure 11.41 Clock Generation Block Diagram (USIn, where n = 0 and 1)
Figure 11.42 Synchronous Mode SCKn Timing (USIn , where n = 0 and 1)
Figure 11.43 Frame Format (USI0/1)
Figure 11.44 Asynchronous Start Bit Sampling (USIn, where n = 0 and 1)
Figure 11.46 Stop Bit Sampling and Next Start Bit Sampling (USIn, where n = 0 and 1)
Table 11-18 CPOLn Functionality (where n = 0 and 1)
Figure 11.47 USI0/1 SPI Clock Formats when CPHAn=0 (where n = 0 and 1)
Figure 11.48 USI0/1 SPI Clock Formats when CPHAn=1 (where n = 0 and 1)
Figure 11.49 USI0/1 SPI Block Diagram (where n = 0 and 1)
Figure 11.50 Bit Transfer on the I2C-Bus (USIn, where n = 0 and 1)
Figure 11.51 START and STOP Condition (USIn, where n = 0 and 1)
Figure 11.53 Acknowledge on the I2C-Bus (USIn, where n = 0 and 1)
Figure 11.54 Clock Synchronization during Arbitration Procedure (USIn, where n = 0 and 1)
Figure 11.56 Formats and States in the Master Transmitter Mode (USIn, where n = 0 and 1)
Figure 11.57 Formats and States in the Master Receiver Mode (USIn, where n = 0 and 1)
Figure 11.58 Formats and States in the Slave Transmitter Mode (USIn, where n = 0 and 1)
Figure 11.59 Formats and States in the Slave Receiver Mode (USIn, where n = 0 and 1)
Figure 11.60 USI0/1 I2C Block Diagram (where n = 0 and 1)
Table 11-19 USI0/1 Register Map (where n = 0 and 1)
Baud Rate setting (example)
Bit A/D Converter
Figure 11.61 12-bit ADC Block Diagram
Figure 11.64 ADC Operation for Align Bit
Figure 11.65 A/D Converter Operation Flow
Power Down Operation
IDLE Mode
STOP Mode
Release Operation of STOP Mode
Table 12-2 Power Down Operation Register Map
RESET
RESET Noise Canceller
Figure 13.5 Configuration Timing when Power-on
Table 13-2 Boot Process Description
External RESETB Input
Brown Out Detector Processor
LVI Block Diagram
Table 13-3 Reset Operation Register Map
On-chip Debug System
Two-Pin External Interface
Figure 14.3 Data Transfer on the Twin Bus
Figure 14.5 Start and Stop Condition
Figure 14.7 Clock Synchronization during Wait Procedure
Figure 14.8 Connection of Transmission
Flash Memory
Figure 15.1 Flash Program ROM Structure
Table 15-1 Flash Memory Register Map
Configure Option
APPENDIX
MC97F2664
12
Apr
il 11
, 20
14 Ver. 1.4
1.3
Ordering Information
Table 1-1 Ordering Information of MC97F2664
Device name
ROM size
IRAM size
XRAM size
Package
MC97F2664L
64k bytes FLASH
256 bytes
4,096 bytes
64 LQFP-1010
MC97F2664L14
64 LQFP-1414
MC97F2664UB
64 QFN
MC97F2464Q
44 MQFP-1010
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