Advantech ARK-3400 User Manual

Contents

ARK-3400 User Manual 303.2.4 Advanced Chipset FeaturesFigure 3.4 Award BIOS Advanced Chipset Features DRAM Timing Selectable [By SPD]This item allows the user to set optimal timings for items 2 through 5. The sys-tem default setting of “By SPD” follows the SPD information on the ROM chipand ensures the system runs stably, with optimal performance. CAS Latency Time [Auto]This item allows the user to set the timing delay in clock cycles before SDRAMstarts a read command after receiving it. DRAM RAS# to CAS# Delay [Auto]This item allows the user to set the timing of the transition from RAS (rowaddress strobe) to CAS (column address strobe) as both rows and columns areseparately addressed shortly after the DRAM is refreshed. DRAM RAS# Precharge [Auto]This item allows the user to set the DRAM RAS# precharge timing. The systemdefault is set to “Auto” to reference the data from the SPD ROM. Precharge delay (tRAS) [Auto]This item allows the user to adjust memory precharge time. System Memory Frequency [Auto]This item allows the user to adjust memory frequency to improve performance. SLP_S4# Assertion Width [4 to 5 sec.]This item allows user to adjust SLP_S4# signal.This field indicates the mini-mum assertion width of the SLP_S4# signal to ensure that the DRAMs havebeen safely power-cycled. System BIOS Cacheable [Enabled]This item allows the system BIOS to be cached to allow faster execution andbetter performance. Video BIOS Cacheable [Disabled]Note! This “Advanced Chipset Features” screen controls the configuration ofthe board’s chipset for fine-tuning system performance. Screen optionsdepend on the specific chipset. It is strongly recommended that onlytechnical users make changes to the default settings.