— 71 —PIN NAME I/O DESCRIPTIONMA [9:0]MD [63:0]~WE~RAS~CAS~CS0~DQM[7:0]DSFBASDCKSDCKEN~ROMENOI/OOOOOOOOI/OI/OOExternal Memory Address Bus. The video memory row and column addresses are multiplexed on theselines.External Memory Data BusExternal Memory Write StrobeExternal Memory SDRAM Row Address SelectExternal SGRAM Column Address SelectExternal SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MBmemoryExternal SGRAM I/O mask [7:0]. DQM [7:0] are byte specific. DQM0 masks MD [7:0], DQM1 masks MD[15:8],Ö,and DQM7 masks MD [63:58].External SGRAM Block writeExternal SGRAM Bank Select. SDRAM has dual internal banks. Bank address defines to which bank thecurrent command is being applied.External SGRAM clock. SDCK is driven by the memory clock. All SDRAM input signals are sampled on thepositive edge of SDCK.External SGRAM clock enable. SDCKEN activates (HIGH) and deactivates (LOW) the SDCLK signal.Deactivating the SDCK provides POWER-DOWN and SELF-REFRESH mode.ROM EnableExternal Display Memory InterfaceFlat Panel InterfaceFDATA[23:0]LP/FHSYNCFP/FVSYNCM/DEFPSCLKFPENFPVDDENVBIASENOOOOOOOOFlat Panel Data bit 23 to bit 0. Note: For SM712, the upper 12 bits [25:24] are multiplexed with ZV port, andthe upper 12 bits [23:11] are dedicated for flat panel dataDSTN LCD: Line PulseTFT LCD: LCD Horizontal SyncDSTN LCD: Frame PulseTFT LCD: LCD vertical syncM-signal or Display Enable. This signal is used to indicate the active horizontal display time.FPR3E [7] is used to select1 = M-signal0 = Display EnableFlat Panel Shift Clock. This is the pixel clock for Flat Panel Data.Flat Panel Enable. This signal needs to become active after all panel voltages, clocks, and data aresupplied. This signal also needs to become inactive before any panel voltages or control signals areremoved. FPEN is part of the VESA FPDI-1B specification.Flat Panel VDD Enable. This signal is used to control LCD logic power.Flat Panel Voltage Bias Enable. This signal is used to control LCD Bias power.