Dell External OEMR R810 Technical Manual

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Dell External OEMR R810 Technical Manual Manual pdf 33 page image

DellDell PowerEdge R810 Technical Guide 327.8 62BMemory RAS SupportThe Intel Xeon processor 6500 and 7500 series supports high-availability memory modes includingrank and DIMM sparing as well as memory mirroring. The R810 supports rank sparing only andmirroring as shown in Table 8.Table 8. PowerEdge R810 Sparing and MirroringSparing MirroringType Rules enforced 1P 2P 4P Rules EnforcedRank The capacity of the sparerank must be greaterthan that of any otherrank on the channelNo support Inter-socket(hemispheremodeenabled)Inter-socket32 DIMM only,Mirrored must match7.8.1 114BSparingFor Rank sparing, one rank on each lockstep Intel 7500 SMB pair will be reserved as a spare, and inthe event that another rank exceeds a threshold of correctable ECC errors, the ―failing‖ rank will becopied to the spare. Once that operation is complete, the failed rank will be disabled.7.8.2 115BMirroringFor mirroring, the R810 will support 2P/4P configurations with 32 DIMMs only. When mirroring isenabled, only half of the physical memory will be visible to the system software. A full copy of thememory is maintained, and in the event of an uncorrectable error, the system will switch over to themirrored copy. In 2P mode, the mirroring will be inter-node with hemisphere mode enabled. In thiscase, the memory controller (MBox) of CPU1 is mapped to the corresponding MBox of CPU2. Thefigure below depicts the mirroring logic for 2P configurations. A, B, C and D represent the DIMMsocket groups.Figure 16. PowerEdge R810 2P MirroringFor 4-processor configurations, the PowerEdge R810 will also support mirroring in the inter-socketmode (note that intra-socket is not possible in 4P because each CPU has only one MBox connected tomemory buffers). In this 4P case, the memory on CPU1 will be mirrored with memory on CPU3, whilememory on CPU2 is mirrored with memory on CPU4. Figure 17 depicts the mirroring logic for 2Pconfigurations. A,B,C and D represent the DIMM socket groups.CPU1MBOX0MBOX1CPU2MBOX0MBOX1DIMM1DIMM2DIMM3DIMM4DIMM5DIMM6DIMM7DIMM8ADIMM1DIMM2DIMM3DIMM4DIMM5DIMM6DIMM7DIMM8CDIMM1DIMM2DIMM3DIMM4DIMM5DIMM6DIMM7DIMM8DDIMM1DIMM2DIMM3DIMM4DIMM5DIMM6DIMM7DIMM8B