Dell External OEMR T610 Technical Manual

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Dell External OEMR T610 Technical Manual Manual pdf 34 page image

DellPowerEdge T610 Technical Guide 348 Chipset8.1 OverviewThe PowerEdge T610 planar incorporates the Intel® Xeon® 5520 processor series chipset for I/O andprocessor interfacing. This chipset is designed to support the Intel Xeon 5500 and 5600 processorseries family, QuickPath Interconnect, DDR3 memory technology, and PCI Express Generation 2. Thechipset consists of the Intel 5520 chipset I/O Hub (IOH) and ICH9.8.2 Intel I/O Hub (IOH)The planar uses the Intel 5520 chipset IOH to provide a link between the Intel Xeon processor series5500 and 5600 processor(s) and the I/O components. The main components of the IOH consist of twofull-width QuickPath Interconnect links (one to each processor), 36 lanes of PCI Express Gen2, a x4Direct Media Interface (DMI), and an integrated IOxAPIC.8.3 IOH QuickPath Interconnect (QPI)The QuickPath Architecture consists of serial point-to-point interconnects for the processors and theIOH. The T610 has a total of three QuickPath Interconnect (QPI) links—one link connecting theprocessors, and multiple links connecting both processors with the IOH. Each link consists of 20 lanes(full-width) in each direction with a link speed of 6.4 GT/s. An additional lane is reserved for aforwarded clock. Data is sent over the QPI links as packets.The QuickPath Architecture implemented in the IOH and processors features four layers: Physical layer—Consists of the actual connection between components. Supports PolarityInversion and Lane Reversal for optimizing component placement and routing. Link layer—Responsible for flow control and the reliable transmission of data. Routing layer—Responsible for the routing of QPI data packets. Protocol layer—Responsible for high-level protocol communications, including theimplementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherenceprotocol.8.4 Intel Direct Media Interface (DMI)The DMI connects the Intel 5520 chipset IOH with the Intel I/O Controller Hub (ICH). The DMI isequivalent to a x4 PCIe Gen1 link with a transfer rate of 1 GB/s in each direction.8.5 PCI ExpressPCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles thesignaling bit rate of each lane from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible with Gen1 transfer rates.The IOH has two x2 PCIe Gen2 ports (1 GB/s) and eight x4 PCIe Gen2 ports (2 GB/s). The x2 ports canbe combined as a x4 link; however, this x4 link cannot be combined with any of the other x4 ports.Two neighboring x4 ports can be combined as a x8 link, and both resulting x8 links can combine toform a x16 link.8.6 Intel I/O Controller Hub 9 (ICH9)ICH9 is a highly integrated I/O controller, supporting the following functions: Six x1 PCIe Gen1 ports, with the capability of combining ports 1-4 as a x4 link (ports areunused on T610) PCI Bus 32-bit Interface Rev 2.3 running at 33 MHz