Dell External OEMR XL R610 Technical Manual

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Dell External OEMR XL R610 Technical Manual Manual pdf 32 page image

DellPowerEdge R610 Technical Guide 328 ChipsetThe PowerEdge R610 planar incorporates the Intel® Xeon® 5500 processor series chipset for I/O andprocessor interfacing. This chipset is designed to support the Intel Xeon 5500 and 5600 processorseries family, QuickPath Interconnect, DDR3 memory technology, and PCI Express Generation 2. Thechipset consists of the Intel 5500 chipset I/O Hub (IOH) and ICH9.8.1 Intel I/O Hub (IOH)The planar uses the Intel 5500 chipset IOH to provide a link between the Intel Xeon processor series5500 and 5600 processor(s) and the I/O components. The main components of the IOH consist of twofull-width QuickPath Interconnect links (one to each processor), 24 lanes of PCI Express Gen2, a x4Direct Media Interface (DMI), and an integrated IOxAPIC.8.2 IOH QuickPath Interconnect (QPI)The QuickPath Architecture consists of serial point-to-point interconnects for the processors and theIOH. The R610 has a total of three QuickPath Interconnect (QPI) links—one link connecting theprocessors, and multiple links connecting both processors with the IOH. Each link consists of 20 lanes(full-width) in each direction with a link speed of 6.4 GT/s. An additional lane is reserved for aforwarded clock. Data is sent over the QPI links as packets.The QuickPath Architecture implemented in the IOH and processors features four layers: Physical layer—This layer consists of the actual connection between components. It supportsPolarity Inversion and Lane Reversal for optimizing component placement and routing. Link layer—This layer is responsible for flow control and the reliable transmission of data. Routing layer—This layer is responsible for the routing of QPI data packets. Protocol layer—This layer is responsible for high-level protocol communications, including theimplementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherenceprotocol.8.3 IOH PCI ExpressPCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles thesignaling bit rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports arebackwards-compatible with Gen1 transfer rates.The IOH has 24 PCI Express lanes. The lanes are partitioned as two x2 PCI Express Gen2 ports andeight x4 PCI Express Gen2 ports. The x2 ports can be combined as a x4 link; however, this x4 linkcannot be combined with any of the other x4 ports. Two neighboring x4 ports can be combined as ax8 link, and both resulting x8 links can combine to form a x16 link.8.4 Intel I/O Controller Hub 9 (ICH9)ICH9 is a highly integrated I/O controller, supporting the following functions: Six x1 PCI Express Gen1 ports, with the capability of combining ports 1-4 as a x4 link (R610uses the x4 link for storage, the other two x1 lanes go unused) PCI Bus 32-bit Interface Rev 2.3 running at 33 MHz Up to six Serial ATA (SATA) ports with transfer rates up to 300 MB/s (R610 supports one SATAport for an optional internal optical drive) Six UHCI and two EHCI (high-speed 2.0) USB host controllers, with up to 12 USB ports Four external USB ports and one internal USB port