Table 2. Processor and Heat Sink ConfigurationsProcessorConfigurationProcessorType (inWatts)HeatSinkNumber of DIMMsMaximum Reliability, Availability, andServiceability (RAS) FeaturesTwo processors Up to 95W67 mm 24 (Three DIMMs perchannel) 24 (Three DIMMs per channel)Two processors Above 95W87 mm 20 (Three DIMMs inchannels 0 and 3 and twoDIMMs in channels 1 and2)16 (Two DIMMs per channel)Four processors Up to 95W67 mm 48 48Four processors Above 95W87 mm 40 (Three DIMMs inchannels 0 and 3 and twoDIMMs in channels 1 and2)32 (Two DIMMs per channel)Mode-Specific GuidelinesFour memory channels are allocated to each processor. The allowable configurations depend on thememory mode selected.NOTE: x4 and x8 DRAM based DIMMs can be mixed providing support for RAS features. However,all guidelines for specific RAS features must be followed. x4 DRAM based DIMMs retain SingleDevice Data Correction (SDDC) in memory optimized (independent channel) mode. x8 DRAM basedDIMMs require Advanced ECC mode to gain SDDC.The following sections provide additional slot population guidelines for each mode.Advanced ECC (Lockstep)Advanced ECC mode extends SDDC from x4 DRAM based DIMMs to both x4 and x8 DRAMs. Thisprotects against single DRAM chip failures during normal operation.Memory installation guidelines:• Memory modules must be identical in size, speed, and technology.• DIMMs installed in memory sockets with white release tabs must be identical and similar rule appliesfor sockets with black and green release tabs. This ensures that identical DIMMs are installed inmatched pairs - for example, A1 with A2, A3 with A4, A5 with A6, and so on.NOTE: Advanced ECC with Mirroring is not supported.Memory Optimized (Independent Channel) ModeThis mode supports SDDC only for memory modules that use x4 device width and does not impose anyspecific slot population requirements.Memory SparingNOTE: To use memory sparing, this feature must be enabled in the System Setup.In this mode, one rank per channel is reserved as a spare. If persistent correctable errors are detected ona rank, the data from this rank is copied to the spare rank and the failed rank is disabled.56