DellPowerEdge M910 Technical Guide 24Model Speed TDP Power Cache Cores QPI SpeedE7540 2.00GHz 105W 18M 6 6.4GT/sE6540 2.00GHz 105W 18M 6 6.4GT/sE7530 1.86GHz 105W 12M 6 5.86GT/sE6510 1.73GHz 105W 12M 4 4.8GT/sL7555 1.86GHz 95W 24M 8 5.86GT/sL7545 1.86GHz 95W 18M 6 5.86GT/sE7520 1.86GHz 95W 18M 4 4.8GT/s6.4 Processor ConfigurationsThe Dell™ PowerEdge™ M910 is designed to support either a dual processor configuration withFlexMem Bridge or a four-processor configuration. In either configuration, all I/O and memory isavailable in the system. While not formally supported, single processor configurations with aprocessor installed in CPU1 will allow the system to boot for diagnostic purposes.The Intel Xeon E7-2800 product family and Intel Xeon processor 6500 series are for two-socketconfigurations only and cannot be upgraded to four-socket configurations.6.5 FlexMem BridgeIn a four-processor configuration, the PowerEdge M910 uses only one memory controller perprocessor. This single controller connects to two memory buffers via Intel SMI links. Each memorybuffer in turn connects to four DDR3 DIMMs. In a typical Intel Xeon processor 6500 or 7500 seriesconfiguration, only the memory buffers associated with the two populated sockets would beconnected, and therefore only 16 DIMMs would be accessible.To overcome this limitation with two processors, the M910 uses the FlexMem Bridge which allowsCPU1 and CPU2 to connect to the memory of their respective adjacent sockets (CPU3 and CPU4). TheFlexMem Bridge provides the following: Two pass-through links for SMI One pass-through link for QPIThe pass-through SMI links connect the two installed processors to additional SMIs, therefore theprocessors will have the following memory attached: CPU1 has access to DIMMs [A1:A8] and DIMMs [C1:C8] (those normally associatedwith CPU3) CPU2 has access to DIMMs [B1:B8] and DIMMs [D1:D8] (those normally associatedwith CPU4)The pass-through QPI link on the FlexMem Bridge provides increased performance for a 2Pconfiguration because it allows 2 full-bandwidth QPI links between CPU1 and CPU2 as opposed to asingle link. Figure 4 depicts the interconnection between the CPU sockets as well as connectionsinternal to the FlexMem Bridges. The FlexMem Bridges are only supported in sockets 3 and 4.