Dell PowerEdge T110 II Technical Manual

Also see for PowerEdge T110 II: Portfolio guide Owner's manual Technical guide Important information Getting started guide

Dell PowerEdge T110 II Technical Manual Manual pdf 27 page image

PowerEdge T110 II Technical Guide 278 Chipset8.1 OverviewThe PowerEdge T110 II planar incorporates the Intel® C200 Series PCH chipset. The features listedbelow are part of the chipset.8.2 Direct Media InterfaceDirect Media Interface (DMI) is the chip-to-chip connection between the processor and C200 serieschipset. This high-speed interface integrates advanced priority-based servicing allowing forconcurrent traffic and true isochronous transfer capabilities. Base functionality is completelysoftware-transparent, permitting current and legacy software to operate normally.8.3 PCI Express InterfaceThe C200 series chipset provides up to 8 PCI Express root ports, supporting bandwidths of 2.5 GT/sand 5 GT/s. PCI Express Root Ports 1-4 can be statically configured as four x1 ports or gangedtogether to form one x4 port. Ports 5 and 6 can only be used as two x1 ports.8.4 SATA interfaceThe chipset supports up to six Serial ATA (SATA) ports capable of independent DMA operation. TheSATA controllers are completely software transparent with an IDE interface, providing a lower pincount and higher performance. PCH SATA interface supports data transfer rates up to 3 Gb/s (300MB/s) per port. The SATA controller contains two modes of operation— a legacy mode using I/Ospace and an AHCI mode using memory space.The chipset supports the Serial ATA Specification, Revision 3.0. Additionally, the chipset is capableof supporting data transfer rates up to 3 Gb/s (300 MB/s) external SATA (eSATA) to ease the additionof external high performance storage devices.8.5 AHCIThe C200 series chipset provides hardware support for Advanced Host Controller Interface (AHCI), anew programming interface for SATA host controllers. Platforms supporting AHCI may take advantageof performance features, such as having no master/slave designation for SATA devices—each deviceis treated as a master—and hardware-assisted native command queuing. AHCI also provides usabilityenhancements such as hot-plugging. AHCI requires appropriate software support (an AHCI driver) andfor some features, it requires hardware support in the SATA device or additional platform hardware.8.6 PCI InterfaceThe chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. It integrates a PCI arbiterthat supports up to four external PCI bus masters in addition to the internal chipset requests. Thisallows for combinations of up to four PCI down devices and PCI slots.8.7 Low Pin Count (LPC) InterfaceThe C200 series chipset implements an LPC Interface as described in the LPC 1.1 Specification. TheLow Pin Count (LPC) bridge function of the chipset resides in PCI Device 31: Function 0. In addition tothe LPC bridge interface function, D31:F0 contains other functional units including DMA, interruptcontrollers, timers, power management, system management, GPIO, and RTC.