99ADV7623 Hardware ManualRev. 0 – March 2010 18 Confidential NDA requiredLocation Mnemonic Type DescriptionD in the HDMI interface.27 RXD_0+ HDMI Input Digital input channel 0 True of port D inthe HDMI interface.28 CGND Ground TVDD and CVDD Ground29 RXD_1- HDMI Input Digital input channel 1 complement of portD in the HDMI interface.30 RXD_1+ HDMI Input Digital input channel 1 true of port D in theHDMI interface.31 TVDD Power Receiver terminator supply voltage (3.3 V)32 RXD_2- HDMI Input Digital input channel 2 complement of portD in the HDMI interface.33 RXD_2+ HDMI Input Digital input channel 2 true of port D in theHDMI interface.34 CVDD Power Receiver comparator supply voltage (1.8V)35 CGND Ground TVDD and CVDD Ground36 TXPVDD Power 1.8 V Power Supply for Digital and I/OPower Supply. These pins supply power tothe digital logic and I/Os. They should befiltered and as quiet as possible.37 TXPLVDD Power 1.8 V Power Supply.38 TXGND Ground TXPVDD Ground39 TXPGND Ground TXPLVDD Ground40 EXT_SWING Analog Input Sets Internal Reference Currents. Place 887Ω resistor (1% tolerance) between this pinand ground.41 HPD_ARC- Analog Input Hot Plug Detect Signal. This indicates tothe interface whether the receiver isconnected. Supports 1.8 V to 5.0V CMOSlogic levels.42 ARC+ Analog Input Audio return channel input43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pinserves as the master to the DDC bus.Supports a 5 V CMOS logic level.44 TXDDC_SCL Digital Input Serial Port Data Clock to Receiver. This pinserves as the master clock for the DDC bus.Supports a 5 V CMOS logic level.45 TXAVDD Power 1.8V power supply for TMDS outputs46 TXGND Ground TXAVDD Ground47 TXC- HDMI Output Differential Clock Output. Differentialclock output at the TMDS clock rate;supports TMDS logic level.48 TXC+ HDMI Output Differential Clock Output. Differentialclock output at the TMDS clock rate;supports TMDS logic level.