Denon AVR-E300 Service Manual
Also see for AVR-E300: Owner's manualGetting startedGetting started
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139A3V56S30FTP (DIGITAL : IC833,834 )A3V56S30FTP Pin FunctionA3V56S30FTPA3V56S40FTP256M Single Data Rate Synchronous DRAMRevision 1.1 Mar., 2010Page 2 / 39CLK : Master Clock DQM : Output Disable / Write Mask (A3V56S30FTP)CKE : Clock Enable DQMU,L : Output Disable / Write Mask (A3V56S40FTP)/CS : Chip Select A0-12 : Address Input/RAS : Row Address Strobe BA0,1 : Bank Address/CAS : Column Address Strobe Vdd : Power Supply/WE : Write Enable VddQ : Power Supply for OutputDQ0-7 : Data I/O (A3V56S30FTP) Vss : GroundDQ0-15 : Data I/O (A3V56S40FTP) VssQ : Ground for OutputBA0BA1VddDQ0VddQDQ1DQ2VssQDQ3DQ4VddQDQ5DQ6VssQDQ7VddDQML/WE/CAS/RAS/CSA10(AP)A2A3VddA0A1VddDQ0VddQNCDQ1VssQNCDQ2VddQNCDQ3VssQNCVddNC/WE/CAS/RAS/CSBA0BA1A10(AP)A2A3VddA0A1DQMCKEVssDQ15VssQDQ14DQ13VddQDQ12DQ11VssQDQ10DQ9VddQDQ8VssNCDQMUCLKCKEA12A11A8A7A6A5A4VssA9VssDQ7VssQNCDQ6VddQNCDQ5VssQNCDQ4VddQNCVssNCCLKA12A11A8A7A6A5A4VssA9PIN CONFIGURATION (TOP VIEW)PIN CONFIGURATION(TOP VIEW)x8x16123456789101112131415161718192021225453525150494847464544434241403938373635343323 3224 3125 3026 2927 28A3V56S30FTPA3V56S40FTP256M Single Data Rate Synchronous DRAMNote:This figure shows the A3V56S30FTPThe A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15Type Designation CodeA 3Ｖ 56 Ｓ４０F ＴＰ－G6Speed Grade 75： 133MHz@CL=37： 143MHz@CL=36： 166MHz@CL=3G： GreenPackage Type TP：TSOP (II) |
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