Denon AVR-X1200W Service Manual

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Contents

Denon AVR-X1200W Service Manual Manual pdf 139 page image

M12L64164A-5TG2Y (DIGITAL_DSP : IC784)Block diagramRevision 1.0 Dec., 2012Page 2/39CLK : Master Clock U,LDQM : Output Disable / Write MaskCKE : Clock Enable A0-11 : Address Input/CS : Chip Select BA0,1 : Bank Address/RAS : Row Address Strobe Vdd : Power Supply/CAS : Column Address Strobe VddQ : Power Supply for Output/WE : Write Enable Vss : GroundDQ0-15 : Data I/O VssQ : Ground for OutputBA0BA1VddDQ0VddQDQ1DQ2VssQDQ3DQ4VddQDQ5DQ6VssQDQ7VddLDQM/WE/CAS/RAS/CSA10(AP)A2A3VddA0A1VssDQ15VssQDQ14DQ13VddQDQ12DQ11VssQDQ10DQ9VddQDQ8VssNCUDQMCLKCKENCA11A8A7A6A5A4VssA9PIN CONFIGURATION (TOP VIEW)PIN CONFIGURATION(TOP VIEW)123456789101112131415161718192021225453525150494847464544434241403938373635343323 3224 3125 3026 2927 28ESMT M12L64164A (2Y)FUNCTIONAL BLOCK DIAGRAMPIN FUNCTION DESCRIPTIONPIN NAME INPUT FUNCTIONCLK System Clock Active on the positive going edge to sample all inputsCS Chip Select Disables or enables device operation by masking or enabling allinputs except CLK , CKE and L(U)DQMCKE Clock EnableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior new command.Disable input buffers for power down in standby.A0 ~ A11 Address Row / column address are multiplexed on the same pins.Row address : RA0~RA11, column address : CA0~CA7BA1 , BA0 Bank Select Address Selects bank to be activated during row address latch time.Selects bank for read / write during column address latch time.RAS Row Address StrobeLatches row addresses on the positive going edge of the CLK withRAS low.Enables row access & precharge.CAS Column Address StrobeLatches column address on the positive going edge of the CLK withCAS low.Enables column access.WE Write Enable Enables write operation and row precharge.Latches data in starting from CAS , WE active.L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when L(U)DQM active.DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provideL(U)DQMDQModeRegisterControl Logic ColumnAddressBuffer&RefreshCounterRowAddressBuffer&RefreshCounterBank DRow DecoderBank ABank BBank CSense AmplifierColumn DecoderData Control CircuitLatch CircuitInput & OutputBufferAddressClockGeneratorCLKCKECommand DecoderCSRASCASWE139