1 - 4 IMAGETEAM™ 4X00 Series Integration ManualElectrical Interface ConsiderationsWhen designing the host system circuitry with a switched V In imager, you must make sure there is no leakage path from the hostinto the imager I/O lines. Leakage back into the imager I/O causes the imager VIn to be back powered via the imager’s internalpull-ups, protection diodes, and parasitic FET diodes. This results in unwanted current draw and causes the imager's power upreset system to fail. A power up reset failure causes the imager to behave erratically and it may not respond correctly to I 2Ccommands.11 Vin LED +3V to +9V - Power supply input for LED illumination and aiming.12 D0 Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid onthe rising edge of pixel clock.13 Vin Imager Vin Imager, +3.3V - Power supply for the imager. Care must be taken to ensure this supply is heavilydecoupled and is protected from cross coupling to high frequency signals of the processing/decoding cir-cuitry. A broad band filter may be needed to obtain adequate isolation. See Considerations and Methodsfor the Power Supply on page C-1.When designing the host system circuitry with a switched V In imager, you must guarantee there is noleakage path from the host into the imager I/O lines. Leakage back into the imager I/O causes theimager V In to be back powered via the imager’s internal pull-ups, protection diodes, and parasitic FETdiodes. This results in unwanted current draw and the imager's power up reset system will fail. Theimager behaves erratically and may not respond correctly to I2C commands when there is a power upreset failure.14 D1Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid onthe rising edge of pixel clock.15 D216 D317 D418 D519 D620 D721 Pixel Clock (PCLK) Output - Imager timing signal that clocks pixel data. Data is valid on the rising edge of this signal.Pin Signal Description