4 - 44-2-7 APC CIRCUIT (MAIN UNIT)The APC circuit protects the power amplifier from a mis-matched output load and stabilizes the output power.The APC detector circuit (D14, D17, L39) detects forwardsignals and reflection signals at D14 and D17 respectively.The combined voltage is at minimum level when the anten-na impedance is matched at 50 Ω and is increased when itis mismatched.The detected voltage is applied to the differential amplifier(IC6, pin 2), and the power setting voltage is applied to theother input (pin 1) for the reference.When antenna impedance is mismatched, the detected volt-age exceeds the power setting voltage. The output voltageof the differential amplifier (IC6, pin 1) controls the input cur-rent of the power module (IC10) to reduce the output power.4-3 PLL CIRCUITS4-3-1 PLL CIRCUITA PLL circuit provides stable oscillation of the transmit fre-quency and the receive 1st LO frequency. The PLL circuitcompares the phase of the divided VCO frequency to thereference frequency. The PLL output frequency is controlledby the divided ratio (N-data) of a programmable divider.An oscillated signal from the VCO passes thorough the LOand buffer amplifiers (Q9, Q12) is applied to the PLL IC (IC1,pin 6) and is prescaled in the PLL IC based on the dividedratio (N-data). The reference signal is generated at the ref-erence oscillator (X1) and is also applied to the PLL IC. ThePLL IC detects the out-of-step phase using the referencefrequency and outputs it from pin 15. The output signal ispassed through the loop filter (Q2, R6, R11–R15, C11, C12)and is then applied to the VCO circuit as the lock voltage viathe “LV” line.4-3-2 VCO CIRCUIT (MAIN unit)The VCO circuit contains a separate TX-VCO (Q6, D2, D4)and RX-VCO (Q7, D5, D38). The oscillated signal is ampli-fied at the LO (Q9) and buffer (Q11) amplifiers, and is thenapplied to the T/R switching circuit (D6, D7). Then the Txand Rx signals are applied to the pre-driver (Q17) and 1stmixer (Q19) respectively.A portion of the signal from Q4 is amplified at the bufferamplifier (Q6) and is then fed back to the PLL IC (IC1 pin 2)as the comparison signal.Poweramp.IC6APCamp.Driveramp.+—PredriveHVto the antennaT1TXCIC11Q26, Q39, Q40RF signalT8APC control circuitQ17 Q35 IC10Power detector circuitL39D14 D17• APC CIRCUITShift registerPrescalerPhasedetectorChargepumpLoopfilterProgrammabledividerReferencedividerX121.25 MHz1LOBufferBuffer234PLLCKPLLDATAPLLSTBto transmitter circuitto 1st mixer circuitD6D7Q11Q12Q99 6Q6, D2, D4TX VCOQ7, D5RX VCOIC1 LV2105V21.25 MHz 2nd LO signalto the FM IF IC (IC4, pin 2)16LPFLPF• PLL CIRCUIT