4 - 1SECTION 4 CIRCUIT DESCRIPTION4-1 RECEIVER CIRCUITS4-1-1 ANTENNA SWITCHING CIRCUIT(MAIN UNIT)The antenna switching circuit functions as a low-pass filterwhile receiving and a resonator circuit while transmitting.The circuit does not allow transmit signals to enter receivercircuits.Received signals enter the antenna connector and passthrough the low-pass filter (L47, L48, C208, C210, C217).The filtered signals are passed through the λ/4 type anten-na switching circuit (D16, D19, L45, L46) and limiter circuits(D15). The signals are then applied to the squelch attenua-tor circuit.4-1-2 SQUELCH ATTENUATOR CIRCUIT(MAIN UNIT)The attenuator circuit attenuates the signal strength to amaximum of 10 dB to protect the RF amplifier from distortionwhen excessively strong signals are received.The current flow of the antenna switching circuit (D16, D19)is controlled by the [SQL] control via the attenuator con-troller (IC6a, D18). When the [SQL] control is rotated clock-wise deeper than 12 o’clock, the current of D16 and D19 isincreased. In this case, D16 and D19 act as an attenuator.4-1-3 RF CIRCUIT (MAIN UNIT)The RF circuit amplifies signals within the range of frequen-cy coverage and filters out-of-band signals.The signals from the squelch attenuator circuit pass throughthe tunable bandpass filter (D13). The filtered signals areamplified at the RF amplifier (Q27) and then enter anotherthree-stage bandpass filters (D9–D11) to suppress unwant-ed signals. The filtered signals are applied to the 1st mixercircuit (Q19).The tunable bandpass filters (D13–D16) employ varactordiodes to tune the center frequency of the RF passband forwide bandwidth receiving and good image response rejec-tion. These diodes are controlled by the CPU (LOGIC unit;IC1) via the D/A convertor (IC5).4-1-4 1ST MIXER AND 1ST IF CIRCUITS(MAIN UNIT)The 1st mixer circuit converts the received signals to a fixedfrequency of the 1st IF signal with the PLL output frequency.By changing the PLL frequency, only the desired frequencywill pass through a pair of crystal filters at the next stage ofthe 1st mixer.The RF signals from the bandpass filter are applied to the1st mixer circuit (Q19). The applied signals are mixed withthe 1st LO signal coming from the RX-VCO circuit (Q7, D5,D38) to produce a 21.7 MHz 1st IF signal. The 1st IF signalpasses through a pair of crystal filters (FI3, FI4) to suppressout-of-band signals. The filtered signal is amplified at the 1stIF amplifier (Q16), and applied to the 2nd IF circuit via thelimiter circuit (D29).4-1-5 2ND IF AND DEMODULATOR CIRCUITS(MAIN unit)The 2nd mixer circuit converts the 1st IF signal to a 2nd IFsignal. A double-conversion superheterodyne systemimproves the image rejection ratio and obtains stable receiv-er gain.The 1st IF signal from the IF amplifier (Q16) is applied to the2nd mixer section of the FM IF IC (IC4, pin 16) and is thenmixed with the 2nd LO signal for conversion to a 450 kHz2nd IF signal.IC4 contains the 2nd mixer, limiter amplifier, quadraturedetector, S-meter detector, active filter and noise amplifiercircuits, etc. A frequency from the PLL reference oscillator isused for the 2nd LO signal (21.25 MHz).Mixer16Limiteramp.2nd IF filter450 kHz(for wide)(for narrow)X121.25 MHzIC4 TA31136FN12 1st IF from theIF amplifier (Q16)"SD" signal to the CPU(FRONT unit; IC1, pin 4)111098Q37, Q387AF signal "DETO"R5VX22ActivefilterNoisedetectorFMdetector13"NOIS" signal to the CPU(FRONT unit; IC1, pin 26)RSSINoisecomp.PLL ICIC1 116"SQLIN" signal fromthe D/A converter IC(IC5, pin 11)AMdetectorIC12AM/FMselectorFI23FI1• 2ND IF AND DEMODULATOR CIRCUIT