Icom IC-F2610 Service Manual

Also see for IC-F2610: Instruction manual Service manual Service manual

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Icom IC-F2610 Service Manual Manual pdf 11 page image

4 - 44-3 PLL CIRCUITS4-3-1 PLL CIRCUIT (MAIN UNIT)A PLL circuit provides stable oscillation of the transmit fre-quency and receive 1st LO frequency. The PLL circuit con-sists of the PLL IC, charge pump, loop filter and referenceoscillator and employs a pulse swallow counter.Oscillated signals from the VCO via the buffer amplifiers(Q19, Q18) are prescaled in the PLL IC (IC12, pin 11) basedon the divided ratio (N-data). The PLL IC detects the out-of-step phase using the reference frequency and outputs itfrom pin 6 (IC12). The output signal is passed through thecharge pump (Q30–Q33) and loop filters (R154/C181,R153/C179), and is then applied to the VCO circuit as thelock voltage.The accelerator switch (IC13) selects the effective loop filterto accelerate the PLL lock up speed.The lock voltage is also used for the receiver tunable band-pass filters to match the filter’s center frequency to thedesired receive frequency. The lock voltage is amplified atthe buffer amplifier (Q29) and is then applied to the band-pass filters (D7–D11, D514) as center frequency control sig-nal.4-3-2 VCO CIRCUIT (MAIN UNIT)The VCO circuit contains a separate Rx VCO (Q21, D19,D20) and Tx VCO (Q23, D21, D22, D46). The oscillated sig-nal is amplified at the buffer amplifiers (Q19, Q20) and isthen applied to the T/R switches (D17, D18). Then thereceive 1st LO (Rx) signal is applied to the 1st mixer (Q2) viathe LO amplifier (Q3) and the transmit (Tx) signal to the dri-ver (Q17).A portion of the signal from the buffer amplifier (Q19) is fedback to the PLL IC (IC12, pin 11) via the another bufferamplifier (Q18) as the comparison signal.Shift registerPrescalerPhasedetectorLoopfilterProgrammablecounterProgrammabledividerBufferBufferBuffer Q20Q18Q19171819PSTBIC12 (PLL IC)PCKPDAto transmitter circuitto 1st mixer circuitD17D18206 11X50112.6 MHzRx VCOQ21,D19, D20Tx VCOQ23,D21, D22, D46Chargepump• PLL CIRCUITLINEHVVCCCPU5V+5V+8VR8VT8VMT8VFVPP+18VDESCRIPTIONThe voltage from the external power connector.Same voltage as the HV line passed through thepower control circuit (Q12, Q14) controlled byPWON signal from the CPU (IC20, pin 77).Common 5 V converted from the HV line at the5V regulator circuit (IC17). This voltage is sup-plied to the CPU regardless of the power switch.Common 5 V converted from the VCC line at the+5V regulator circuit (Q42, Q43, D30) using theCPU5V line voltage as the reference.Common 8 V converted from the VCC line at the+8V regulator circuit (IC16).Receive 8 V converted from the VCC line at theR8V regulator circuit (Q36, Q37, D27) using the+8V line voltage as the reference and controlledby VRX signal from the CPU (IC20, pin 76).Transmit 8 V converted from the VCC line at theT8V regulator circuit (Q40, Q41, D29) using the+8V line voltage as the reference and controlledby VTX signal from the the CPU (IC20, pin 75).Transmit 8 V converted from the VCC line at theMT8V regulator circuit (Q38, D28) using the +8Vline voltage as the reference and controlled byTMUT signal from the the CPU (IC20, pin 62).Common 12 V converted from the +12V regula-tor circuit (IC506, Q508, Q509) using the VCCline. The circuit is controlled by the FVPC linefrom the CPU (IC20, pin 10).Common 18 V converted from the +18V DC/DCconvertor circuit (IC18, Q44, D31–D33) usingthe +8V line. The output voltage is applied to thebuffer amplifier (Q29) and loop filter (IC13,Q30–Q33).4-4 POWER SUPPLY CIRCUITVOLTAGE LINE