4 - 64-6 PORT ALLOCATIONSCPU (MAIN UNIT; IC20)20212224253031323840434447, 4849505153555625576062PTTOPTTIAFONBUSYPOSWMMUTRMUTNOISAFVRSSICDECCENCECS2,ECS1ECKESIESOBEEPMCONAMUTNWCHFSWPATMUTOutputs the PTT control signal.Low : While transmittingInput port for the PTT control signalfrom PTTO port.Input port for the AF amplifier ON sig-nal from an optional unit.Outputs busy signal for an optionalunit.Input port for the power switch.Low : While power switch is pushedInput port for microphone audio mutecontrol signal from an optional unit.Input port for receive audio mute con-trol signal from an optional unit.Input port for noise signals (pulse-type) for noise squelch operation.Input port for the volume control.Input port for receiving signal strengthlevel detection.Input port for CTCSS/DTCS decoding.Output ports for CTCSS/DTCS sig-nals.Output ports for EEPROM select sig-nals.ECS1: For internal EEPROM (IC27)ECS2: For optional EEPROMOutputs clock signal for EEPROMs.Input port for serial signal fromEEPROMs.Outputs serial signal for EEPROMs.Outputs beep audio signals.Outputs mic. audio mute control signalto the audio switch (IC25).High : While DTMF signals are beingtransmitted, etc.Outputs the AF mute switch (Q6) con-trol signal.High : While squelched, etc.Outputs N/W switch control signals.High : While wide is selectedOutputs high-pass filter’s characteris-tics select signal.High : During CTCSS operationOutputs mic. audio select signal to theaudio switch (IC25).High : While “Public-address” func-tion is ONOutputs MT8V regulator circuit (Q38,D27) control signal.High : While transmit is muted.646566676869727375767778798082–899399DSTBDDADCKPSTBPDAPCKUNLKPLLTVTXVRXPWONPASPSPDIMDTR1–DTR4,DTC4–DTC1HORNSIFTOutputs strobe signals for the levelcontroller. (IC5)Outputs data signal for the level con-troller (IC5).Outputs clock signal for the level con-troller (IC5).Outputs strobe signals for the PLL IC(IC12).Outputs data signal for the PLL IC(IC12).Outputs clock signal for the PLL IC(IC12).Input port for the PLL unlock signal.High : During unlockOutputs PLL accelerator control signal.High : While scanning, etc.Outputs the T8V regulator circuit (Q38,D28) control signal.Low : While transmittingOutputs the R8V regulator circuit(Q36, D27) control signal.Low : While receivingOutputs the power control circuit (Q12)control signal.High : During power ONOutputs “Public-address” mute signal.High : While PA and Ext. SP func-tions are not usedOutputs the mute switch (Q7) controlsignal (incl. beep).High : While squelched, etc.Input port for an external LCD back-light brightness control signal.Low : LCD backlight is dimmedOutputs DTMF audio signals.Outputs high level control signal for thepre-set time to the connected externalunit when matched 2- or 5-tone code isreceived.Outputs CPU clock shift signal.Pin Port Descriptionnumber namePin Port Descriptionnumber name