Icom IC-F3GT Service Manual

Also see for IC-F3GS: Instruction manual Instruction manual Instruction manual User manual Service manual

Contents

Icom IC-F3GT Service Manual Manual pdf 10 page image

4 - 3When the driving current is increased, input voltage of thedifferential amplifier (pin 2) will be increased. In such cases,the differential amplifier output voltage (pin 1) is decreasedto reduce the driving current.4-3 PLL CIRCUITA PLL circuit provides stable oscillation of the transmit fre-quency and receive 1st LO frequency. The PLL output com-pares the phase of the divided VCO frequency to the refer-ence frequency. The PLL output frequency is controlled bythe divided ratio (N-data) of a programmable divider.The PLL circuit contains the VCO circuit (Q7, Q8). The oscil-lated signal is amplified at the buffer-amplifiers (Q6, Q5) andthen applied to the PLL IC (IC1, pin 2).The PLL IC contains a prescaler, programmable counter,programmable divider and phase detector, etc. The enteredsignal is divided at the prescaler and programmable countersection by the N-data ratio from the CPU. The divided signalis detected on phase at the phase detector using the refer-ence frequency.If the oscillated signal drifts, its phase changes from that ofthe reference frequency, causing a lock voltage change tocompensate for the drift in the oscillated frequency.A portion of the VCO signal is amplified at the buffer-ampli-fier (Q4) and is then applied to the receive 1st mixer (Q13)or transmit buffer-amplifier circuit (Q3) via the T/R switchingdiode (D3, D4).4-4 POWER SUPPLY CIRCUITSVOLTAGE LINE• PLL circuitShift register×2PrescalerPhasedetectorLoopfilterProgrammablecounterProgrammabledividerX115.3 MHz30.6 MHz signalto the FM IF IC"DEV" signal from theD/A convertor (IC10, pin 22)when transmitting16Q7, Q8VCO circuitBufferQ6BufferQ4BufferQ5345PLSTSCKSOto transmitter circuitto 1st mixer circuitD4D3178 2LINEHVVCC5VT5R5S5OPTDESCRIPTIONThe voltage from the attached battery pack.The same voltage as the HV line (battery volt-age) which is controlled by the power swtich([VOL] control).Common 5 V converted from the VCC line by thereference regulator circuit (IC6). The output volt-age is applied to the CPU (IC8), the 5 V regula-tor circuit (Q18, Q19) and reset circuit (IC11).5 V for transmitter circuits regulated by the T5regulator circuit (Q22).5 V for receiver circuits regulated by the R5 reg-ulator circuit (Q21).Common 5 V converted from the VCC line by theS5 regulator circuit (Q18, Q19).The same voltage as the 5V line for the optionalHM-46L, EM-71 or HS-51 through a resistor(R132).