Icom IC-PCR100 Service Manual

Also see for COMMUNICATION RECEIVER IC PCR100: Instruction manual

Contents

4 - 54-2-3 2ND LO LOOPThe 2nd LO circuit generates the 2nd LO frequencies, andthe signals are applied to the 2nd mixer circuit.The generated signal at the VCO 3 (Q34) enters the PLL IC(IC8, pin 13) via the buffer amplifier (Q35), is divided ath theprogrammable divider seiction and is then applied to thephase detector section.The phase detector compares the input signal with a refer-ence frequency, and then outputs the out-of-phase signal(pulse-type signals) from pin17The pulse-type signal is converted into DC voltage (lockvoltage) at the loop filter (Q36, Q37), and then applied to theVCO 3 to stabilize the oscillated frequency.4-3 POWER SUPPLY CIRCUITS4-3-1 VOLTAGE LINESDescriptionThe voltage from a DC power supply.The same voltage as the ACHV line which iscontrolled by the [POWER] switch.Common 5 V line converted from the HV line bythe +5 regulator circuit (IC16).Common 8 V line converted from the HV line bythe +8 regulator circuit (IC17).Common 33 V line converted from the HV line bythe 33 V DC-DC convertor circuit (IC18). Theoutput voltage is applied to the PLL circuit.Common 5 V line converted from the ACHV lineby the L+5 regulator circuit (IC15).LineACHVHV+5+8+33L+5• PLL circuitLoopfilterLoopfilter BufferAmp.Amp.BufferBufferQ36, Q37Q25, Q26Q35Q27Q22Q24IC6IC26Q34D72–D74Q14, Q15D39, D40Q18, Q19D42, D43to 1st mixer circuit1st LO-freq.:532.4–1066.65 MHz2nd LO-freq.:255–257 MHz1st LO-freq.:266.7–532.35 MHzto 2nd mixer circuitL1AD to the CPU1/2ATTATT LPFLPFBPFLPFVCO1VCO3VCO2X512.8 MHzShift register/data latchPLL IC (IC8)PrescalerPhasedetectorProgrammablecounterPrescalerPhasedetectorProgrammablecounterProgrammabledividerPdatPckPSTB